Power-centric design of high-speed I/Os

With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitt...

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Veröffentlicht in:2006 43rd ACM/IEEE Design Automation Conference S. 867 - 872
Hauptverfasser: Hatamkhani, Hamid, Lambrecht, Frank, Stojanovic, Vladimir, Yang, Chih-Kong Ken
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: New York, NY, USA ACM 24.07.2006
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Aggregates
Algorithms
Bandwidth
Bit error rate
Channel Model
Circuit noise
Convex Optimization
Design
Hardware > Emerging technologies
Hardware > Integrated circuits > Interconnect > Input > output circuits
Hardware > Very large scale integration design
I/O
Jitter
Noise level
Power dissipation
Power Minimization
Serial Link
Signal design
Standardization
Transmitters
Voltage
power minimization
I/O
convex optimization
serial link
channel model
ISBN:1595933816, 9781595933812
ISSN:0738-100X
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Abstract With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitter, slew rate, BER etc. These specifications lead to complex tradeoffs for both circuits and circuit architecture in order to minimize power. This paper presents a design framework that enables the analysis of tradeoffs in the design of an I/O transmitter. The design framework includes BER analysis with a channel model coupled with logic sizing optimization that is constrained by the desired signaling specification.
AbstractList With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitter, slew rate, BER etc. These specifications lead to complex tradeoffs for both circuits and circuit architecture in order to minimize power. This paper presents a design framework that enables the analysis of tradeoffs in the design of an I/O transmitter. The design framework includes BER analysis with a channel model coupled with logic sizing optimization that is constrained by the desired signaling specification.
Author Yang, Chih-Kong Ken
Lambrecht, Frank
Stojanovic, Vladimir
Hatamkhani, Hamid
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  givenname: Hamid
  surname: Hatamkhani
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  organization: UCLA, Newport Coast, CA
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  givenname: Frank
  surname: Lambrecht
  fullname: Lambrecht, Frank
  organization: Rambus Inc., Los Altos, CA
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  givenname: Vladimir
  surname: Stojanovic
  fullname: Stojanovic, Vladimir
  organization: MIT, Cambridge, MA
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  givenname: Chih-Kong Ken
  surname: Yang
  fullname: Yang, Chih-Kong Ken
  organization: UCLA, Los Angeles, CA
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Keywords power minimization
I/O
convex optimization
serial link
channel model
Language English
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Snippet With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design...
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StartPage 867
SubjectTerms Aggregates
Algorithms
Bandwidth
Bit error rate
Channel Model
Circuit noise
Convex Optimization
Design
Hardware -- Emerging technologies
Hardware -- Integrated circuits -- Interconnect -- Input -- output circuits
Hardware -- Very large scale integration design
I/O
Jitter
Noise level
Power dissipation
Power Minimization
Serial Link
Signal design
Standardization
Transmitters
Voltage
Title Power-centric design of high-speed I/Os
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