Low complexity LDPC code decoders for next generation standards
This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder archite...
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| Vydáno v: | 2007 Design, Automation & Test in Europe Conference & Exhibition : Nice, France, 16-20 April 2007 s. 331 - 336 |
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| Hlavní autoři: | , , , , , , , , |
| Médium: | Konferenční příspěvek |
| Jazyk: | angličtina |
| Vydáno: |
San Jose, CA, USA
EDA Consortium
16.04.2007
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| Edice: | ACM Conferences |
| Témata: | |
| ISBN: | 3981080122, 9783981080124 |
| On-line přístup: | Získat plný text |
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| Shrnutí: | This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture. |
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| Bibliografie: | SourceType-Conference Papers & Proceedings-1 ObjectType-Conference Paper-1 content type line 25 |
| ISBN: | 3981080122 9783981080124 |
| DOI: | 10.5555/1266366.1266437 |