System Level Design and Verification Using a Synchronous Language
Synchronous languages such as Esterel, Lustre, Signal, andothers were originally developed for safety-critical embedded software and compiled into C. They have recently been extended to hardware with new language features and compilers to RTL. Contrary to traditional HDL languages (Verilog, VHDL) an...
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| Shrnutí: | Synchronous languages such as Esterel, Lustre, Signal, andothers were originally developed for safety-critical embedded software and compiled into C. They have recently been extended to hardware with new language features and compilers to RTL. Contrary to traditional HDL languages (Verilog, VHDL) and recent system-level languages (SystemC, System Verilog), they have well defined formal semantics,which facilitate bug avoidance using correct-by-constructioncompilation and verification techniques.The tutorial will demonstrate what the synchronous language offers for the modeling, design, analysis and implementation of systems that comprise hardware and software.It will be based on Esterel. Esterel models have proved tobe useful for rapid design space exploration and verificationat system level, without resorting to detailed implementation and slow bit-level event-based simulation. We show how to model control-dominated IP blocks at a higher levelof abstraction and how to use the target C code or RTL inconjunction with other system-level tools. Case studies include examples of design space exploration by synthesizing equivalent hardware or software from the same Esterel description, with formal verification of safety properties such as bus protocol conformance. We conclude with a review of future research directions. |
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| Bibliografie: | SourceType-Conference Papers & Proceedings-1 ObjectType-Conference Paper-1 content type line 25 |
| ISBN: | 9781581137620 1581137621 |
| ISSN: | 1092-3152 |
| DOI: | 10.5555/996070.1009926 |