Graph-partitioning based instruction scheduling for clustered processors

This work presents a novel scheme to schedule loops for clustered microarchitectures. The scheme is based on a preliminary cluster assignment phase implemented through graph partitioning techniques followed by a scheduling phase that integrates register allocation and spill code generation. The grap...

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Bibliographic Details
Published in:Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture pp. 150 - 159
Main Authors: Aletà, Alex, Codina, Josep M., Sánchez, Jesús, González, Antonio
Format: Conference Proceeding Journal Article
Language:English
Published: Washington, DC, USA IEEE Computer Society 01.01.2001
Series:ACM Conferences
Subjects:
ISBN:0769513697, 9780769513690
ISSN:1072-4451
Online Access:Get full text
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