Graph-partitioning based instruction scheduling for clustered processors

This work presents a novel scheme to schedule loops for clustered microarchitectures. The scheme is based on a preliminary cluster assignment phase implemented through graph partitioning techniques followed by a scheduling phase that integrates register allocation and spill code generation. The grap...

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Bibliographic Details
Published in:Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture pp. 150 - 159
Main Authors: Aletà, Alex, Codina, Josep M., Sánchez, Jesús, González, Antonio
Format: Conference Proceeding Journal Article
Language:English
Published: Washington, DC, USA IEEE Computer Society 01.01.2001
Series:ACM Conferences
Subjects:
Software and its engineering
Software and its engineering > Software notations and tools
Software and its engineering > Software notations and tools > Compilers
Theory of computation
Theory of computation > Design and analysis of algorithms
Theory of computation > Design and analysis of algorithms > Approximation algorithms analysis
Theory of computation > Design and analysis of algorithms > Approximation algorithms analysis > Scheduling algorithms
Theory of computation > Design and analysis of algorithms > Online algorithms
Theory of computation > Design and analysis of algorithms > Online algorithms > Online learning algorithms
Theory of computation > Design and analysis of algorithms > Online algorithms > Online learning algorithms > Scheduling algorithms
Theory of computation > Models of computation
Theory of computation > Models of computation > Concurrency
Theory of computation > Models of computation > Concurrency > Parallel computing models
Theory of computation > Theory and algorithms for application domains
Theory of computation > Theory and algorithms for application domains > Machine learning theory
Theory of computation > Theory and algorithms for application domains > Machine learning theory > Reinforcement learning
Theory of computation > Theory and algorithms for application domains > Machine learning theory > Reinforcement learning > Sequential decision making
ISBN:0769513697, 9780769513690
ISSN:1072-4451
Online Access:Get full text
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Summary:This work presents a novel scheme to schedule loops for clustered microarchitectures. The scheme is based on a preliminary cluster assignment phase implemented through graph partitioning techniques followed by a scheduling phase that integrates register allocation and spill code generation. The graph partitioning scheme is shown to be very effective due to its global view of the whole code while the partition is generated. Results show a significant speedup when compared with previously proposed techniques. For some processor configuration the average speedup for the SPECfp95 is 23% with respect to the published scheme with the best performance. Besides, the proposed scheme is much faster (between 2-7 times, depending on the configuration).
Bibliography:SourceType-Scholarly Journals-2
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ObjectType-Conference Paper-1
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SourceType-Conference Papers & Proceedings-1
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ISBN:0769513697
9780769513690
ISSN:1072-4451
DOI:10.5555/563998.564019