Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells

With the continued scaling of VLSI technology beyond 3 nm, a consistent demand for layout reduction in standard cells has been made. CFET (Complementary-FET) has been accepted as a promising device technology, stacking N-FET on P-FET (or vice versa) to achieve this goal while providing metal interco...

Full description

Saved in:
Bibliographic Details
Published in:2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
Main Authors: Ahn, Jaehoon, Kim, Taewhan
Format: Conference Proceeding
Language:English
Published: IEEE 22.06.2025
Subjects:
CFET
DTCO
FFET
Integrated circuit interconnections
Logic gates
Metals
Optimization
Physical design
Pins
Resource management
Routing
standard cells
Wire
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:With the continued scaling of VLSI technology beyond 3 nm, a consistent demand for layout reduction in standard cells has been made. CFET (Complementary-FET) has been accepted as a promising device technology, stacking N-FET on P-FET (or vice versa) to achieve this goal while providing metal interconnects on both the front and backside of the wafer through BEOL (back-end-of-line) processing. However, the layout synthesis of CFET based standard cells and its use in physical design implementation are not fully compatible with the effective exploitation of backside interconnects. This is because of a considerable overhead on the allocation of special vias in FEOL (front-end-of-line) referred to as tap-cells, which are essential for the net routes using backside wire. To overcome this drawback of using CFET cells, a new technology called FFET (Flip-FET) has been proposed, which flips the lower FET in CFET to enable direct pin accessibility on both sides of BEOL with no tap cells. In this context, we propose an FFET cell based DTCO methodology to fully utilize backside wires with minimal tap-cells. Precisely, we propose a three-step approach: (1) synthesizing multiple FFET standard cells with diverse styles of pin distribution for each of primitive logic gates, (2) performing a tap-cell avoiding cell replacement during placement optimization by using the cells obtained from Step 1 to prevent tap-cell allocation for net routing, and (3) rebalancing the wire usage between the frontside and backside to mitigate net congestion. Experiments with benchmark circuits show that our FFET cell based DTCO methodology scales up chip size beyond CFET designs with much fewer routing failures.
DOI:10.1109/DAC63849.2025.11132817