Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs

To fully harness emerging computing architectures, compilers must provide intuitive input handling alongside powerful code optimization to unlock maximum performance. Coarse-Grained Reconfigurable Arrays (CGRAs) - highly energy-efficient for nested-loop applications - have lacked a compiler capable...

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Bibliographic Details

Published in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
Main Authors:	Lou, Jiahang, Zhu, Qilong, Dai, Yuan, Zhong, Zewei, Yin, Wenbo, Wang, Lingli
Format:	Conference Proceeding
Language:	English
Published:	IEEE 22.06.2025
Subjects:	Bridges CGRA compiler Edge computing Energy efficiency Hardware loop transformation Optimization Pipeline processing Program processors Programming Scalability Source coding
Online Access:	Get full text
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