ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions

Modern data-driven applications expose limitations of von Neumann architectures-extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require data transfers. Existing compute in- and nearmemory solutions mitigate these issues b...

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Bibliographic Details
Published in:2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors: Petrolo, Vincenzo, Guella, Flavia, Caon, Michele, Schiavone, Pasquale Davide, Masera, Guido, Martina, Maurizio
Format: Conference Proceeding
Language:English
Published: IEEE 22.06.2025
Subjects:
custom ISA extensions
Edge Computing
Energy efficiency
Extensibility
Faces
In-cache computing
Instruction sets
Memory architecture
Process control
RISC-V
Synchronization
Throughput
Usability
Vectors
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Summary:Modern data-driven applications expose limitations of von Neumann architectures-extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require data transfers. Existing compute in- and nearmemory solutions mitigate these issues but face usability challenges due to data placement constraints. We propose a novel cache architecture that doubles as a tightly-coupled compute-near-memory coprocessor. Our RISC-V cache controller executes custom instructions from the host CPU using vector operations dispatched to near-memory vector processing units within the cache memory subsystem. This architecture abstracts memory synchronization and data mapping from application software while offering software-based Instruction Set Architecture extensibility. Our implementation shows 30 \times to 84 \times performance improvement when operating on 8-bit data over the same system with a traditional cache when executing a worst-case 32-bit CNN workload, with only 41.3% area overhead.
DOI:10.1109/DAC63849.2025.11132598