Invited: Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations

IC test methodologies all generate scan tests based on logical stuck-at and timing fault models that assume only a single passive physical defect localized at some circuit node. However, transistors fabricated in advanced technologies are subject to increasing random process variations that can sign...

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Veröffentlicht in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) S. 1 - 4
Hauptverfasser:	Singh, Adit D., Faridi, Mukarram Ali
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 22.06.2025
Schlagworte:	Circuit Simulation Delays Digital circuits Integrated circuit modeling Integrated circuit reliability Nonlinear circuits Path Delay Testing Performance evaluation Random processes Silent Error Corruption Testing Threshold voltage Timing Failures Transistors
Online-Zugang:	Volltext
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