ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation

Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo have emerged. However, these models often struggle with instruction alignment, a crucial capability for LLMs that involves...

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Veröffentlicht in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) S. 1 - 7
Hauptverfasser:	Deng, Chenhui, Bai, Yunsheng, Ren, Haoxing
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 22.06.2025
Schlagworte:	Benchmark testing Chip scale packaging Design automation Fuses Hardware Interpolation Large language models Manifolds Merging Translation
Online-Zugang:	Volltext
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