APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design

DNN accelerators, significantly advanced by model compression and specialized dataflow techniques, have marked considerable progress. However, the frequent access of highprecision partial sums (PSUMs) leads to excessive memory demands in architectures utilizing input/weight stationary dataflows. Tra...

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Bibliographic Details

Published in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
Main Authors:	Tan, Yonghao, Dong, Pingcheng, Wu, Yongkun, Liu, Yu, Liu, Xuejiao, Luo, Peng, Liu, Shih-Yang, Huang, Xijie, Zhang, Dong, Liang, Luhong, Cheng, Kwang-Ting
Format:	Conference Proceeding
Language:	English
Published:	IEEE 22.06.2025
Subjects:	Additives Costs dataflow DNN Energy consumption Hardware-aware quantization Large language models Memory architecture Model compression partial sum quantization Power demand Quantization (signal) Reconfigurable architectures Transformer Transformers
Online Access:	Get full text
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