Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design

SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours. During simulation, assertion failures occur when the design's behaviour deviates from expectations. Solving these...

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Vydané v:	2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori:	Zhou, Jie, Ji, Youshu, Wang, Ning, Hu, Yuchen, Jiao, Xinyao, Yao, Bingkun, Fang, Xinwei, Zhao, Shuai, Guan, Nan, Jiang, Zhe
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 22.06.2025
Predmet:	Data augmentation Design automation Hardware Large language models Measurement Register transfer level Reliability Timing Training Training data
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