Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery
As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing cells with multi-VT (threshold voltage) is known to be a very effective method for optimizing leakage power under timing constraints. However, f...
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| Veröffentlicht in: | 2025 62nd ACM/IEEE Design Automation Conference (DAC) S. 1 - 2 |
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22.06.2025
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| Abstract | As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing cells with multi-VT (threshold voltage) is known to be a very effective method for optimizing leakage power under timing constraints. However, for the sequential cells on the timing critical paths in circuits, there is no easy way for the multi-VT method to reduce the leakage power unless timing is not sacrificed. To overcome this barrier, we introduce a set of new standard cells called hybrid-VT flipflop cells, each of which is implemented with two different VT types, one implanted onto its master latch while the other onto its slave latch, by which the setup time and clock-to-Q delay can be controlled individually and independently. We confirm that applying our power recovery method utilizing hybrid-VT flipflop cells to the benchmark circuits, which have already been optimized by the conventional multi-VT cells, is able to further reduce the leakage power by 8.97% with no timing degradation. |
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| AbstractList | As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing cells with multi-VT (threshold voltage) is known to be a very effective method for optimizing leakage power under timing constraints. However, for the sequential cells on the timing critical paths in circuits, there is no easy way for the multi-VT method to reduce the leakage power unless timing is not sacrificed. To overcome this barrier, we introduce a set of new standard cells called hybrid-VT flipflop cells, each of which is implemented with two different VT types, one implanted onto its master latch while the other onto its slave latch, by which the setup time and clock-to-Q delay can be controlled individually and independently. We confirm that applying our power recovery method utilizing hybrid-VT flipflop cells to the benchmark circuits, which have already been optimized by the conventional multi-VT cells, is able to further reduce the leakage power by 8.97% with no timing degradation. |
| Author | Kim, Taewhan Chung, Sehyeon Lee, Jaeha Kang, Kunhyuk Hwang, Hyun-Chul Kim, Byung Su |
| Author_xml | – sequence: 1 givenname: Sehyeon surname: Chung fullname: Chung, Sehyeon email: shchung@snucad.snu.ac.kr organization: Seoul National University,School of Electrical and Computer Engineering,South Korea – sequence: 2 givenname: Hyun-Chul surname: Hwang fullname: Hwang, Hyun-Chul email: h_c.hwang@samsung.com organization: System LSI,Division, Samsung Electronics,South Korea – sequence: 3 givenname: Byung Su surname: Kim fullname: Kim, Byung Su email: bs2014.kim@samsung.com organization: System LSI,Division, Samsung Electronics,South Korea – sequence: 4 givenname: Jaeha surname: Lee fullname: Lee, Jaeha email: jaehayo.lee@samsung.com organization: Foundry Division, Samsung Electronics,South Korea – sequence: 5 givenname: Kunhyuk surname: Kang fullname: Kang, Kunhyuk email: kunhyuk.kang@samsung.com organization: Samsung Austin Research Center,USA – sequence: 6 givenname: Taewhan surname: Kim fullname: Kim, Taewhan email: tkim@snucad.snu.ac.kr organization: Seoul National University,School of Electrical and Computer Engineering,South Korea |
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| Snippet | As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing... |
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| SubjectTerms | Circuits Degradation Delays Design automation design-technology co-optimization flip-flop Flip-flops Hybrid power systems Latches lowpower design Main-secondary standard cell Threshold voltage threshold voltages |
| Title | Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery |
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