Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery

As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing cells with multi-VT (threshold voltage) is known to be a very effective method for optimizing leakage power under timing constraints. However, f...

Full description

Saved in:
Bibliographic Details
Published in:2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 2
Main Authors: Chung, Sehyeon, Hwang, Hyun-Chul, Kim, Byung Su, Lee, Jaeha, Kang, Kunhyuk, Kim, Taewhan
Format: Conference Proceeding
Language:English
Published: IEEE 22.06.2025
Subjects:
Circuits
Degradation
Delays
Design automation
design-technology co-optimization
flip-flop
Flip-flops
Hybrid power systems
Latches
lowpower design
Main-secondary
standard cell
Threshold voltage
threshold voltages
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing cells with multi-VT (threshold voltage) is known to be a very effective method for optimizing leakage power under timing constraints. However, for the sequential cells on the timing critical paths in circuits, there is no easy way for the multi-VT method to reduce the leakage power unless timing is not sacrificed. To overcome this barrier, we introduce a set of new standard cells called hybrid-VT flipflop cells, each of which is implemented with two different VT types, one implanted onto its master latch while the other onto its slave latch, by which the setup time and clock-to-Q delay can be controlled individually and independently. We confirm that applying our power recovery method utilizing hybrid-VT flipflop cells to the benchmark circuits, which have already been optimized by the conventional multi-VT cells, is able to further reduce the leakage power by 8.97% with no timing degradation.
DOI:10.1109/DAC63849.2025.11132590