Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving

The Circuit Satisfiability (CSAT) problem, a variant of the Boolean Satisfiability (SAT) problem, plays a critical role in integrated circuit design and verification. However, existing SAT solvers, optimized for Conjunctive Normal Form (CNF), often struggle with the intrinsic complexity of circuit s...

Celý popis

Podrobná bibliografia

Vydané v:	2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori:	Shi, Zhengyuan, Tang, Tiebing, Zhu, Jiaying, Khan, Sadaf, Zhen, Hui-Ling, Yuan, Mingxuan, Chu, Zhufei, Xu, Qiang
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 22.06.2025
Predmet:	Benchmark testing Complexity theory Design automation Integrated circuit synthesis Logic Optimization Reinforcement learning Runtime Table lookup Technological innovation
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!