Parallelizing CAD a timely research agenda for EDA

The relative decline of single-threaded processor performance, coupled with the ongoing shift towards on chip parallelism requires that CAD applications run efficiently on parallel microprocessors. We believe that an ad hoc approach to parallelizing CAD applications will not lead to satisfactory res...

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Bibliographic Details
Published in:2008 45th ACM/IEEE Design Automation Conference pp. 12 - 17
Main Authors: Catanzaro, Bryan, Keutzer, Kurt, Su, Bor-Yiing
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 08.06.2008
IEEE
Series:ACM Conferences
Subjects:
ISBN:1605581151, 9781605581156
ISSN:0738-100X
Online Access:Get full text
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Summary:The relative decline of single-threaded processor performance, coupled with the ongoing shift towards on chip parallelism requires that CAD applications run efficiently on parallel microprocessors. We believe that an ad hoc approach to parallelizing CAD applications will not lead to satisfactory results: neither in terms of return on engineering investment nor in terms of the computational efficiency of end applications. Instead, we propose that a key area of CAD research is to identify the design patterns underlying CAD applications and then build CAD application frameworks that aid efficient parallel software implementations of these design patterns. Our initial results indicate that parallel patterns exist in a broad range of CAD problems. We believe that frameworks for these patterns will enable CAD to successfully capitalize on increased processor performance through parallelism.
ISBN:1605581151
9781605581156
ISSN:0738-100X
DOI:10.1145/1391469.1391475