Application-transparent near-memory processing architecture with memory channel network

The physical memory capacity of servers is expected to increase drastically with the deployment of the forthcoming non-volatile memory technologies. This is a welcomed improvement for the emerging data-intensive applications. For such servers to be cost-effective, nonetheless, we must cost-effective...

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Bibliographic Details
Published in:2018 51st Annual IEEE ACM International Symposium on Microarchitecture (MICRO) pp. 802 - 814
Main Authors: Alian, Mohammad, Min, Seung Won, Asgharimoghaddam, Hadi, Dhar, Ashutosh, Wang, Dong Kai, Roewer, Thomas, McPadden, Adam, O'Halloran, Oliver, Chen, Deming, Xiong, Jinjun, Kim, Daehoon, Hwu, Wen-mei, Kim, Nam Sung
Format: Conference Proceeding
Language:English
Published: Piscataway, NJ, USA IEEE Press 20.10.2018
IEEE
Series:ACM Conferences
Subjects:
Application Transparent
Bandwidth
Buffer Device
Computer architecture
Distributed Systems
DRAM
Ethernet
General and reference
General and reference > Cross-computing tools and techniques
General and reference > Cross-computing tools and techniques > Performance
Hardware
Memory Channel
Mobile Processors
Near Memory Processing
Processing In Memory
Random access memory
Servers
TCP IP
ISBN:9781538662403, 153866240X
Online Access:Get full text
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Summary:The physical memory capacity of servers is expected to increase drastically with the deployment of the forthcoming non-volatile memory technologies. This is a welcomed improvement for the emerging data-intensive applications. For such servers to be cost-effective, nonetheless, we must cost-effectively increase compute throughput and memory bandwidth commensurate with the increase in memory capacity without compromising the application readiness. Tackling this challenge, we present Memory Channel Network (MCN) architecture in this paper. Specifically, first, we propose an MCN DIMM, an extension of a buffered DIMM where a small but capable processor called MCN processor is integrated with a buffer device on the DIMM for near-memory processing. Second, we implement device drivers to give the host and MCN processors in a server an illusion that they are independent heterogeneous nodes connected through an Ethernet link. These allow the host and MCN processors in a server to run a given data-intensive application together based on popular distributed computing frameworks such as MPI and Spark without any change in the host processor hardware and its application software, while offering the benefits of high-bandwidth and low-latency communication between the host and MCN processors over the memory channels. As such, MCN can serve as an application-transparent framework which can seamlessly unify the near-memory processing within a server and the distributed computing across such servers for data-intensive applications. Our simulation running the full software stack shows that a server with 8 MCN DIMMs offers 4.56 x higher throughput and consume 47.5% less energy than a cluster with 9 conventional nodes connected through Ethernet links, as it facilitates up to 8.17 x higher aggregate DRAM bandwidth utilization. Lastly, we demonstrate the feasibility of MCN with an IBM POWER8 system and an experimental buffered DIMM.
ISBN:9781538662403
153866240X
DOI:10.1109/MICRO.2018.00070