SMT-based bounded model checking for multi-threaded software in embedded systems

The transition from single-core to multi-core processors has made multi-threaded software an important subject over the last years in computer-aided verification. Model checkers have been successfully applied to discover subtle errors, but they suffer from combinatorial state space explosion when ve...

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Vydané v:2010 ACM/IEEE 32nd International Conference on Software Engineering Ročník 2; s. 373 - 376
Hlavný autor: Cordeiro, Lucas
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: New York, NY, USA ACM 01.05.2010
IEEE
Edícia:ACM Conferences
Predmet:
Computational modeling
computer-aided verification
Embedded software
Encoding
formal software verification
General and reference > Cross-computing tools and techniques > Verification
Instruction sets
Multicore processing
multicore systems
SAT modulo theories
Software algorithms
Software and its engineering > Software creation and management > Software development process management
Software and its engineering > Software creation and management > Software verification and validation > Formal software verification
Software and its engineering > Software organization and properties > Software functional properties > Formal methods > Software verification
Theory of computation > Semantics and reasoning > Program reasoning > Program verification
SAT modulo theories
formal software verification
computer-aided verification
multicore systems
ISBN:9781605587196, 1605587192
ISSN:0270-5257
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Popis
Shrnutí:The transition from single-core to multi-core processors has made multi-threaded software an important subject over the last years in computer-aided verification. Model checkers have been successfully applied to discover subtle errors, but they suffer from combinatorial state space explosion when verifying multi-threaded software. In our previous work, we have extended the encodings from SMT-based bounded model checking (BMC) to provide more accurate support for program verification and to use different background theories and solvers in order to improve scalability and precision in a completely automatic way. We now focus on extending this work to support an SMT-based BMC formulation of multithreaded software which allows the state space to be reduced by abstracting the number of state variables and interleavings from the proof of unsatisfiability generated by the SMT solvers. The core idea of our approach aims to extract the proof objects produced by the SMT solvers in order to control the number of interleavings and to remove logic that is not relevant to a given property. This work aims to develop a new algorithmic method and corresponding tools based on SMT to verify embedded software in multi-core systems.
ISBN:9781605587196
1605587192
ISSN:0270-5257
DOI:10.1145/1810295.1810396