Yao, W., Shi, Y., He, L., & Pamarti, S. (2009, November). Joint design-time and post-silicon optimization for digitally tuned analog circuits. 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, 725-730. https://doi.org/10.1145/1687399.1687534
Chicago-Zitierstil (17. Ausg.)Yao, Wei, Yiyu Shi, Lei He, und S. Pamarti. "Joint Design-time and Post-silicon Optimization for Digitally Tuned Analog Circuits." 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Nov. 2009: 725-730. https://doi.org/10.1145/1687399.1687534.
MLA-Zitierstil (9. Ausg.)Yao, Wei, et al. "Joint Design-time and Post-silicon Optimization for Digitally Tuned Analog Circuits." 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, Nov. 2009, pp. 725-730, https://doi.org/10.1145/1687399.1687534.