Optimizing shared cache behavior of chip multiprocessors

One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work well in the CMP case as data accesses from multiple cores can create conflicts in...

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Vydáno v:2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) s. 505 - 516
Hlavní autoři: Kandemir, Mahmut, Muralidhara, Sai Prashanth, Narayanan, Sri Hari Krishna, Zhang, Yuanrui, Ozturk, Ozcan
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 12.12.2009
IEEE
Edice:ACM Conferences
Témata:
Algorithm
Algorithm design and analysis
Computer languages
Costs
Design
Energy consumption
Experimentation
Hardware > Integrated circuits > Semiconductor memory > Dynamic memory
Job shop scheduling
Laboratories
Manufacturing
Permission
Processor scheduling
Software and its engineering > Software notations and tools > Compilers
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ISBN:9781605587981, 1605587982
ISSN:1072-4451
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Shrnutí:One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work well in the CMP case as data accesses from multiple cores can create conflicts in the shared cache space. The main contribution of this paper is a compiler directed code restructuring scheme for enhancing locality of shared data in CMPs. The proposed scheme targets the last level shared cache that exist in many commercial CMPs and has two components, namely, allocation, which determines the set of loop iterations assigned to each core, and scheduling, which determines the order in which the iterations assigned to a core are executed. Our scheme restructures the application code such that the different cores operate on shared data blocks at the same time, to the extent allowed by data dependencies. This helps to reduce reuse distances for the shared data and improves on-chip cache performance. We evaluated our approach using the Splash-2 and Parsec applications through both simulations and experiments on two commercial multi-core machines. Our experimental evaluation indicates that the proposed data locality optimization scheme improves inter-core conflict misses in the shared cache by 67% on average when both allocation and scheduling are used. Also, the execution time improvements we achieve (29% on average) are very close to the optimal savings that could be achieved using a hypothetical scheme.
ISBN:9781605587981
1605587982
ISSN:1072-4451
DOI:10.1145/1669112.1669176