Optimizing shared cache behavior of chip multiprocessors

One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work well in the CMP case as data accesses from multiple cores can create conflicts in...

Full description

Saved in:

Bibliographic Details
Published in:	2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) pp. 505 - 516
Main Authors:	Kandemir, Mahmut, Muralidhara, Sai Prashanth, Narayanan, Sri Hari Krishna, Zhang, Yuanrui, Ozturk, Ozcan
Format:	Conference Proceeding
Language:	English
Published:	New York, NY, USA ACM 12.12.2009 IEEE
Series:	ACM Conferences
Subjects:	Algorithm Algorithm design and analysis Computer languages Costs Design Energy consumption Experimentation Hardware > Integrated circuits > Semiconductor memory > Dynamic memory Job shop scheduling Laboratories Manufacturing Permission Processor scheduling Software and its engineering > Software notations and tools > Compilers Yarn
ISBN:	9781605587981, 1605587982
ISSN:	1072-4451
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Be the first to leave a comment!