A new SBST algorithm for testing the register file of VLIW processors

Feature size reduction drastically influences permanent faults occurrence in nanometer technology devices. Among the various test techniques, Software-Based Self-Test (SBST) approaches have been demonstrated to be an effective solution for detecting logic defects, although achieving complete fault c...

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Vydáno v:Proceedings of the Conference on Design, Automation and Test in Europe s. 412 - 417
Hlavní autoři: Sabena, Davide, Reorda, Matteo Sonza, Sterpone, Luca
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: San Jose, CA, USA EDA Consortium 12.03.2012
Edice:ACM Conferences
Témata:
Computer systems organization > Architectures > Parallel architectures > Very long instruction word
Computer systems organization > Architectures > Serial architectures > Complex instruction set computing
Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing
Hardware > Hardware test
Hardware > Hardware validation
Hardware > Robustness
very long instruction word processors
software-based self test
fault simulation
testing
ISBN:3981080181, 9783981080186
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Shrnutí:Feature size reduction drastically influences permanent faults occurrence in nanometer technology devices. Among the various test techniques, Software-Based Self-Test (SBST) approaches have been demonstrated to be an effective solution for detecting logic defects, although achieving complete fault coverage is a challenging issue due to the functional-based nature of this methodology. When VLIW processors are considered, standard processor-oriented SBST approaches result deficient since not able to cope with most of the failures affecting VLIW multiple parallel domains. In this paper we present a novel SBST algorithm specifically oriented to test the register files of VLIW processors. In particular, our algorithm addresses the cross-bar switch architecture of the VLIW register file by completely covering the intrinsic faults generated between the multiple computational domains. Fault simulation campaigns comparing previously developed methods with our solution demonstrate its effectiveness. The results show that the developed algorithm achieves a 97.12% fault coverage which is about twice better than previously developed SBST algorithms. Further advantages of our solution are the limited overhead in terms of execution cycles and memory occupation.
ISBN:3981080181
9783981080186
DOI:10.5555/2492708.2492812