Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra
This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapath-oriented designs that implement polynomial computations over fixed-size bit-vectors. When the size (m) of the entire datapath is kept constant, fixed-size bit-vector arithmetic manifests itself...
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| Published in: | ICCAD-2005 : International Conference on Computer Aided Design, November 6-10, 2005, DoubleTree Hotel, San Jose, CA pp. 291 - 296 |
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| Main Authors: | , , , |
| Format: | Conference Proceeding |
| Language: | English |
| Published: |
Washington, DC, USA
IEEE Computer Society
31.05.2005
IEEE ACM |
| Series: | ACM Conferences |
| Subjects: | |
| ISBN: | 078039254X, 9780780392540 |
| Online Access: | Get full text |
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| Summary: | This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapath-oriented designs that implement polynomial computations over fixed-size bit-vectors. When the size (m) of the entire datapath is kept constant, fixed-size bit-vector arithmetic manifests itself as polynomial algebra over finite integer rings of residue classes Z/sub 2//sup m/. The verification problem then reduces to that of checking equivalence of multi-variate polynomials over Z/sub 2//sup m/. This paper exploits the concepts of polynomial reducibility over Z/sub 2//sup m/ and derives an algorithmic procedure to transform a given polynomial into a unique canonical form modulo 2/sup m/. Equivalence testing is then carried out by coefficient matching. Experiments demonstrate the effectiveness of our approach over contemporary techniques. |
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| Bibliography: | SourceType-Conference Papers & Proceedings-1 ObjectType-Conference Paper-1 content type line 25 |
| ISBN: | 078039254X 9780780392540 |
| DOI: | 10.5555/1129601.1129644 |

