Design automation for hybrid CMOS-nonoelectronics crossbars

We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL [5]. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the...

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Vydáno v:2007 IEEE International Symposium on Nanoscale Architectures s. 27 - 32
Hlavní autoři: Kyosun Kim, Ramesh Karri, Orailoglu, Alex
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: Washington, DC, USA IEEE Computer Society 21.10.2007
IEEE
Edice:ACM Conferences
Témata:
Applied computing
Applied computing > Enterprise computing
Automatic Layout Design
CMOL FPGA
Design automation
Social and professional topics
Social and professional topics > Professional topics
Social and professional topics > Professional topics > Computing education
Social and professional topics > Professional topics > Computing education > Computing education programs
Social and professional topics > Professional topics > Computing education > Computing education programs > Computer science education
ISBN:9781424417902, 1424417902
ISSN:2327-8218
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Abstract We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL [5]. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the nanoelectronics hardware resource. Towards automating the CMOL physical design process, we developed a model for the CMOL architecture, formulated the placement and routing problems for the CMOL architecture subject to the unique CMOL specific constraints, and solved it by combining a placement algorithm with a gate assignment algorithm in a loop. We validated the proposed approach by implementing several industrial strength designs.
AbstractList We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL [5]. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the nanoelectronics hardware resource. Towards automating the CMOL physical design process, we developed a model for the CMOL architecture, formulated the placement and routing problems for the CMOL architecture subject to the unique CMOL specific constraints, and solved it by combining a placement algorithm with a gate assignment algorithm in a loop. We validated the proposed approach by implementing several industrial strength designs.
Author Kyosun Kim
Ramesh Karri
Orailoglu, Alex
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  organization: Dept. of Electronic Engineering, University of Incheon, Korea
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  surname: Ramesh Karri
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  organization: Dept, of Electrical&Computer Engineering, Polytechnic University, Brooklyn, NY, USA
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  givenname: Alex
  surname: Orailoglu
  fullname: Orailoglu, Alex
  organization: Dept. of Computer Science&Engineering, University of California, San Diego, La Jolla, USA
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Snippet We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL [5]. The CMOL architecture uses NOR...
We developed the first automatic design system targeting a promising hybrid CMOS-nanoelectronics architecture called CMOL. |5|. The CMOL architecture uses NOR...
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StartPage 27
SubjectTerms Applied computing
Applied computing -- Enterprise computing
Automatic Layout Design
CMOL FPGA
Design automation
Social and professional topics
Social and professional topics -- Professional topics
Social and professional topics -- Professional topics -- Computing education
Social and professional topics -- Professional topics -- Computing education -- Computing education programs
Social and professional topics -- Professional topics -- Computing education -- Computing education programs -- Computer science education
Title Design automation for hybrid CMOS-nonoelectronics crossbars
URI https://ieeexplore.ieee.org/document/4400854
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