Fan-Out Wafer-Level Packaging
This comprehensive guide to fan-out wafer-level packaging (FOWLP) technology compares FOWLP with flip chip and fan-in wafer-level packaging. It presents the current knowledge on these key enabling technologies for FOWLP, and discusses several packaging technologies for future trends. The Taiwan Semi...
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| Hlavní autor: | |
|---|---|
| Médium: | Elektronický zdroj E-kniha |
| Jazyk: | angličtina |
| Vydáno: |
Singapore :
Springer Singapore ,
2018.
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| Vydání: | 1st ed. 2018. |
| Témata: | |
| ISBN: | 9789811088841 |
| On-line přístup: |
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| 008 | 180405s2018 si | s |||| 0|eng d | ||
| 020 | |a 9789811088841 | ||
| 024 | 7 | |a 10.1007/978-981-10-8884-1 |2 doi | |
| 035 | |a CVTIDW09269 | ||
| 040 | |a Springer-Nature |b eng |c CVTISR |e AACR2 | ||
| 041 | |a eng | ||
| 100 | 1 | |a Lau, John H. |4 aut | |
| 245 | 1 | 0 | |a Fan-Out Wafer-Level Packaging |h [electronic resource] / |c by John H. Lau. |
| 250 | |a 1st ed. 2018. | ||
| 260 | 1 | |a Singapore : |b Springer Singapore , |c 2018. | |
| 300 | |a XX, 303 p. 278 illus., 226 illus. in color. |b online resource. | ||
| 500 | |a Engineering | ||
| 505 | 0 | |a Patent Issues of Fan-out Wafer-Level Packaging -- Flip Chip Technology vs. FOWLP -- Fan-In Wafer-Level Packaging vs. FOWLP -- Embedded Chip Packaging -- FOWLP: Chip-First and Die Face-Down -- FOWLP: Chip-First and Die Face-Up -- FOWLP: Chip-Last or RDL-First -- FOWLP: PoP with FOWLP -- Fan-Out Panel-Level Packaging (FOPLP) -- 3D Integration -- Heterogeneous Integration. | |
| 516 | |a text file PDF | ||
| 520 | |a This comprehensive guide to fan-out wafer-level packaging (FOWLP) technology compares FOWLP with flip chip and fan-in wafer-level packaging. It presents the current knowledge on these key enabling technologies for FOWLP, and discusses several packaging technologies for future trends. The Taiwan Semiconductor Manufacturing Company (TSMC) employed their InFO (integrated fan-out) technology in A10, the application processor for Apple's iPhone, in 2016, generating great excitement about FOWLP technology throughout the semiconductor packaging community. For many practicing engineers and managers, as well as scientists and researchers, essential details of FOWLP - such as the temporary bonding and de-bonding of the carrier on a reconstituted wafer/panel, epoxy molding compound (EMC) dispensing, compression molding, Cu revealing, RDL fabrication, solder ball mounting, etc. - are not well understood. Intended to help readers learn the basics of problem-solving methods and understand the trade-offs inherent in making system-level decisions quickly, this book serves as a valuable reference guide for all those faced with the challenging problems created by the ever-increasing interest in FOWLP, helps to remove roadblocks, and accelerates the design, materials, process, and manufacturing development of key enabling technologies for FOWLP. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Nanotechnology. | |
| 650 | 0 | |a Optical materials. | |
| 650 | 0 | |a Electronic materials. | |
| 856 | 4 | 0 | |u http://hanproxy.cvtisr.sk/han/cvti-ebook-springer-eisbn-978-981-10-8884-1 |y Vzdialený prístup pre registrovaných používateľov |
| 910 | |b ZE06549 | ||
| 919 | |a 978-981-10-8884-1 | ||
| 974 | |a andrea.lebedova |f Elektronické zdroje | ||
| 992 | |a SUD | ||
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