High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliabilit...
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| Main Author: | |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Singapore :
Springer Singapore ,
2018.
|
| Edition: | 1st ed. 2018. |
| Series: | Computer Architecture and Design Methodologies,
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| Subjects: | |
| ISBN: | 9789811010736 |
| ISSN: | 2367-3478 |
| Online Access: |
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| LEADER | 00000nam a22000005i 4500 | ||
|---|---|---|---|
| 003 | SK-BrCVT | ||
| 005 | 20220618120526.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 170623s2018 si | s |||| 0|eng d | ||
| 020 | |a 9789811010736 | ||
| 024 | 7 | |a 10.1007/978-981-10-1073-6 |2 doi | |
| 035 | |a CVTIDW10057 | ||
| 040 | |a Springer-Nature |b eng |c CVTISR |e AACR2 | ||
| 041 | |a eng | ||
| 100 | 1 | |a Wang, Zheng. |4 aut | |
| 245 | 1 | 0 | |a High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip |h [electronic resource] / |c by Zheng Wang, Anupam Chattopadhyay. |
| 250 | |a 1st ed. 2018. | ||
| 260 | 1 | |a Singapore : |b Springer Singapore , |c 2018. | |
| 300 | |a XX, 197 p. 104 illus., 72 illus. in color. |b online resource. | ||
| 490 | 1 | |a Computer Architecture and Design Methodologies, |x 2367-3478 | |
| 500 | |a Engineering | ||
| 505 | 0 | |a Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook. | |
| 516 | |a text file PDF | ||
| 520 | |a This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. . | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Computer software-Reusability. | |
| 856 | 4 | 0 | |u http://hanproxy.cvtisr.sk/han/cvti-ebook-springer-eisbn-978-981-10-1073-6 |y Vzdialený prístup pre registrovaných používateľov |
| 910 | |b ZE07337 | ||
| 919 | |a 978-981-10-1073-6 | ||
| 974 | |a andrea.lebedova |f Elektronické zdroje | ||
| 992 | |a SUD | ||
| 999 | |c 275205 |d 275205 | ||