Bits of Knowledge: Combining Probabilistic and Formal Techniques for Secure and Low-Power Hardware Design
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| Title: | Bits of Knowledge: Combining Probabilistic and Formal Techniques for Secure and Low-Power Hardware Design |
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| Authors: | Jansson Valter, Henrik, 1998 |
| Subject Terms: | Computer Architecture, Functional programming, Formal verification, Low-power computing, Probabilistic modeling |
| Description: | Power consumption is a major concern in hardware design. Additionally, power usage can be exploited in side-channel attacks, turning power into a security vulnerability. This thesis lays the groundwork for developing side-channel resistant hardware by developing tools that combine power analysis, formal verification, and probabilistic models in order to rigorously establish security guarantees. We begin by presenting a simple power model for CMOS circuits, computable using BDD-based symbolic simulation. This allows the power consumption to be expressed directly as a function of the circuit inputs, shifting the focus to symbolically representing the input distribution. While there are methods for generating symbolic inputs, they have no guarantees with regards to the distribution of generated vectors. On the other hand, there are methods that do have some guarantee on the distribution, but these do not support symbolic simulation. The latter methods are also restricted to generating uniform distributions. This problem is addressed in one of our papers. We introduce methods for defining arbitrary input distributions in a way that supports symbolic simulation, using BDDs as the core computational tool. Beyond power analysis, these introduced methods are widely applicable in both software and hardware verification. We also discuss the implementation and evaluation of a low-power custom processor for high-level languages, detailing decisions for minimizing energy consumption for both core and memory. This is compared to a low-power RISC-V core running a high-level language in software, showing favorable results for the custom design. |
| File Description: | electronic |
| Access URL: | https://research.chalmers.se/publication/546445 https://research.chalmers.se/publication/546445/file/546445_Fulltext.pdf |
| Database: | SwePub |
Nájsť tento článok vo Web of Science | Abstract: | Power consumption is a major concern in hardware design. Additionally, power usage can be exploited in side-channel attacks, turning power into a security vulnerability. This thesis lays the groundwork for developing side-channel resistant hardware by developing tools that combine power analysis, formal verification, and probabilistic models in order to rigorously establish security guarantees. We begin by presenting a simple power model for CMOS circuits, computable using BDD-based symbolic simulation. This allows the power consumption to be expressed directly as a function of the circuit inputs, shifting the focus to symbolically representing the input distribution. While there are methods for generating symbolic inputs, they have no guarantees with regards to the distribution of generated vectors. On the other hand, there are methods that do have some guarantee on the distribution, but these do not support symbolic simulation. The latter methods are also restricted to generating uniform distributions. This problem is addressed in one of our papers. We introduce methods for defining arbitrary input distributions in a way that supports symbolic simulation, using BDDs as the core computational tool. Beyond power analysis, these introduced methods are widely applicable in both software and hardware verification. We also discuss the implementation and evaluation of a low-power custom processor for high-level languages, detailing decisions for minimizing energy consumption for both core and memory. This is compared to a low-power RISC-V core running a high-level language in software, showing favorable results for the custom design. |
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