Gruian, F., Westmijze, M., Lund University, F. o. E., & Lund University, F. o. E. (2008). VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture. Proceedings of the 23rd Annual Acm Symposium on Applied Computing Symposium on Applied Computing (SAC), 1492. https://doi.org/10.1145/1363686.1364037
Chicago-Zitierstil (17. Ausg.)Gruian, Flavius, Mark Westmijze, Faculty of Engineering Lund University, und Faculty of Engineering Lund University. "VHDL Vs. Bluespec System Verilog: A Case Study on a Java Embedded Architecture." Proceedings of the 23rd Annual Acm Symposium on Applied Computing Symposium on Applied Computing (SAC) 2008: 1492. https://doi.org/10.1145/1363686.1364037.
MLA-Zitierstil (9. Ausg.)Gruian, Flavius, et al. "VHDL Vs. Bluespec System Verilog: A Case Study on a Java Embedded Architecture." Proceedings of the 23rd Annual Acm Symposium on Applied Computing Symposium on Applied Computing (SAC), 2008, p. 1492, https://doi.org/10.1145/1363686.1364037.