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VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture

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Názov: VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture
Autori: Gruian, Flavius, Westmijze, Mark
Prispievatelia: Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Parallel Systems, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Parallella System, Originator, Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Originator
Zdroj: Proceedings of the 23rd Annual Acm Symposium on Applied Computing Symposium on Applied Computing (SAC). :1492-1497
Predmety: Natural Sciences, Computer and Information Sciences, Computer Sciences, Naturvetenskap, Data- och informationsvetenskap (Datateknik), Datavetenskap (Datalogi)
Popis: This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Bluespec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.
Prístupová URL adresa: https://doi.org/10.1145/1363686.1364037
Databáza: SwePub
Popis
Abstrakt:This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Bluespec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.
DOI:10.1145/1363686.1364037