On-chip monitor circuit and semiconductor chip
Gespeichert in:
| Titel: | On-chip monitor circuit and semiconductor chip |
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| Patent Number: | 10776,484 |
| Publikationsdatum: | September 15, 2020 |
| Appl. No: | 15/543501 |
| Application Filed: | January 12, 2016 |
| Abstract: | Provided is an on-chip monitor circuit mounted on a semiconductor chip that is equipped with a security function module for performing a security function process on an input signal and outputting a security function signal, the on-chip monitor circuit comprising a monitor circuit for monitoring signal waveforms of the semiconductor chip, wherein the circuit is provided with a first storage means for storing data that designates a window period in which to perform a test of the semiconductor chip, and a control means for performing control to operate the circuit during the window period, when a prescribed test signal is inputted to the security function module. By using the on-chip monitor circuit in a semiconductor chip of which security is required, security attacks, e.g., a Trojan horse or the like, intended to embed a malicious circuit in the production stage of security function module-equipped semiconductors chips, can be prevented. |
| Inventors: | NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITY (Kobe-shi, Hyogo, JP); TELECOM PARISTECH (Paris, FR) |
| Assignees: | NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITY (Kobe-Shi, Hyogo, JP), TELECOM PARISTECH (Paris, FR) |
| Claim: | 1. An on-chip monitor circuit mounted on a semiconductor chip that is provided with a security function module that performs a security function process on an input signal and outputs a security function signal, the on-chip monitor circuit being provided with a monitor circuit that monitors a signal waveform of the semiconductor chip, wherein the on-chip monitor circuit comprises: a first storage configured to store data that designates a time window during which the semiconductor chip is tested, a second storage configured to store a delay code that has been input, and a controller configured to control such that when a predetermined test signal is input by the security function module the monitor circuit operates during the time window, wherein the controller delays timing of the time window by a delay time corresponding to the delay code. |
| Claim: | 2. The on-chip monitor circuit as claimed in claim 1 , wherein the controller comprises: a counter configured to count clock signals and output count value data after receiving a reset signal, and a comparator configured to compare the count value data and data designating the time window and to cause the monitor circuit to operate when the data match. |
| Claim: | 3. The on-chip monitor circuit as claimed in claim 1 , wherein the time window is the period of time during which there is the most information leakage in the security function module. |
| Claim: | 4. The on-chip monitor circuit as claimed in claim 1 , wherein the delay code indicates a delay amount that designates a timing during which there is the most information leakage from the security function module. |
| Claim: | 5. The on-chip monitor circuit as claimed in claim 1 , wherein the monitor circuit monitors the signal waveform of the substrate potential of the semiconductor chip or the power potential of the security function module. |
| Claim: | 6. The on-chip monitor circuit as claimed in claim 1 , wherein the controller stops operation of the monitor circuit after testing of the semiconductor chip is finished. |
| Claim: | 7. The on-chip monitor circuit as claimed in claim 1 , wherein the controller is rendered logically unrewritable by storing at least one predetermined value from the first storage or the second storage after testing of the semiconductor chip is finished. |
| Claim: | 8. The on-chip monitor circuit as claimed in claim 1 , wherein the security function module is an encryption module. |
| Claim: | 9. A semiconductor chip provided with a security module that performs a security function process on an input signal and outputs a security function signal, wherein the semiconductor chip comprises: an on-chip monitor circuit mounted on the semiconductor, the on-ship monitor circuit being provided with a monitor circuit that monitors a signal waveform of the semiconductor chip, wherein the on-chip monitor circuit comprises: a first storage configured to store data that designates a time window during which the semiconductor chip is test, a second storage configured to store a delay code that has been input, and a controller configured to perform control such that when a predetermined test signal is input by the security function module the monitor circuit operates during the time window, wherein the controller delays timing of the time window by a delay time corresponding to the delay code. |
| Claim: | 10. A semiconductor chip testing system, comprising a semiconductor chip and a testing device that tests the semiconductor chip, wherein the semiconductor chip is provided with a security module that performs a security function process on an input signal and outputs a security function signal, the semiconductor chip comprising an on-chip monitor circuit mounted on the semiconductor, the on-chip monitor circuit being provided with a monitor circuit that monitors a signal waveform of the semiconductor chip, the on-chip monitor circuit comprising: a first storage configured to store data that designates a time window during which the semiconductor chip is tested, a second storage configured to store a delay code that has been input, and a controller configured to perform control such that when a predetermined test signal is input by the security function module the monitor circuit operates during the time window, wherein the controller delays timing of the time window by a delay time corresponding to the delay code, and wherein the testing device is provided with a test signal generator configured to generate a test signal and to deliver said test signal to the semiconductor chip such that a time period of information leakage from the security function module falls within the time window, and an arbiter configured to judge a security score by quantifying information leakage from the security function module on the basis of the signal waveform from the monitor circuit. |
| Claim: | 11. A method for testing a semiconductor chip using an on-chip monitor circuit that is mounted on the semiconductor chip that is provided with a security function module that performs a security function process on an input signal and outputs a security function signal, the on-chip monitor circuit being provided with a monitor circuit that monitors a signal waveform of the semiconductor chip, wherein the method comprises: a step of storing to a first storage data that designates a time window during which the semiconductor chip is tested, a step of storing a delay code that has been input into a second storage, and a step of performing control such that when a predetermined test signal is input by the security function module the monitor circuit operates during the time window, and a step of delaying timing of the time window by a delay time corresponding to the delay code. |
| Claim: | 12. The method for testing a semiconductor chip as claimed in claim 11 , further comprising: a step of generating a test signal and delivering said test signal to the semiconductor chip such that a time period of information leakage from the security function module falls within the time window, and a step of judging a security score by quantifying information leakage from the security function module on the basis of the signal waveform from the monitor circuit. |
| Claim: | 13. The method for testing a semiconductor chip as claimed in claim 11 , further comprising a step of stopping operation of the monitor circuit after testing of the semiconductor chip is finished. |
| Claim: | 14. The method for testing a semiconductor chip as claimed in claim 11 , further comprising a step of producing a logically unrewritable state by storing at least one predetermined value from the first storage or the second storage after testing of the semiconductor chip is finished. |
| Claim: | 15. The method for testing a semiconductor chip as claimed in claim 11 , wherein the security function module is an encryption module. |
| Patent References Cited: | 6298458 October 2001 Cranford, Jr. 7525331 April 2009 Jairam 2002/0130807 September 2002 Hall 2004/0093535 May 2004 Eleyan 2005/0066189 March 2005 Moss et al. 2006/0050929 March 2006 Rast 2007/0011508 January 2007 Rong 2007/0011542 January 2007 Mukherjee 2008/0276111 November 2008 Jacoby et al. 2009/0095955 April 2009 Kim et al. 2009/0295402 December 2009 Balch 2010/0001776 January 2010 Nakamura 2010/0145672 June 2010 Yen 2010/0246808 September 2010 Hisakado et al. 2011/0045323 February 2011 Ooi 2011/0261953 October 2011 Guilley et al. 2012/0200159 August 2012 Katagiri 2013/0070651 March 2013 Nishizaka 2013/0127441 May 2013 Tseng 2015/0323590 November 2015 Xu 2016/0139199 May 2016 Petrie 2016/0274178 September 2016 Goel H05-251523 September 1993 2009-089045 April 2009 10-2004-0049117 June 2004 2014/144857 September 2014 |
| Other References: | Eric Brier et al., “Correlation Power Analysis with a Leakage Model,” CHES 2004, vol. 3156 of LNCS, pp. 16-29, Aug. 2004. cited by applicant Suresh Chari et al., “Template Attacks,” CHES 2002, vol. 2523 of LNCS, pp. 13-28, Aug. 2002. cited by applicant Suvadeep Hajra et al., “SNR to success rate: Reaching the limit of non-profiling DPA,” Cryptology ePrint Archive, Report 2013/865, 2013. cited by applicant Michael Muehlberghuber et al., “Red Team vs. Blue Team Hardware Trojan Analysis, Detection of a Hardware Trojan on an Actual ASIC,” Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy (HASP 2013), Article No. 1, 2013. cited by applicant Daisuke Fujimoto et al., “Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic Chip,” 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 32-37. cited by applicant Paul C. Kocher et al., “Differential Power Analysis,” Proceedings of CRYPTO'99, LNCS, vol. 1666, 1999, pp. 388-397. cited by applicant Laurent Sauvage et al., “Electro-Magnetic Attacks Case Studies on Non-Protected and Protected Cryptographic Hardware Accelerators,” IEEE EMC, Special session #4 on Modeling/Simulation Validation and use of FSV, Jul. 25-30, 2010. cited by applicant U.S. Department Of Defense, “Defense Science Board Task Force on High Performance Microchip Supply,” Feb. 2005, retrieved Dec. 10, 2014 <http://www.acq.osd.mil/dsb/reports/2005-02-HPMS_Report_Final.pdf>. cited by applicant |
| Primary Examiner: | Jamshidi, Ghodrat |
| Attorney, Agent or Firm: | Baker & Hostetler LLP |
| Dokumentencode: | edspgr.10776484 |
| Datenbank: | USPTO Patent Grants |
| Abstract: | Provided is an on-chip monitor circuit mounted on a semiconductor chip that is equipped with a security function module for performing a security function process on an input signal and outputting a security function signal, the on-chip monitor circuit comprising a monitor circuit for monitoring signal waveforms of the semiconductor chip, wherein the circuit is provided with a first storage means for storing data that designates a window period in which to perform a test of the semiconductor chip, and a control means for performing control to operate the circuit during the window period, when a prescribed test signal is inputted to the security function module. By using the on-chip monitor circuit in a semiconductor chip of which security is required, security attacks, e.g., a Trojan horse or the like, intended to embed a malicious circuit in the production stage of security function module-equipped semiconductors chips, can be prevented. |
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