Parallel processing apparatus, parallel computing method, and recording medium storing parallel computing program
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| Titel: | Parallel processing apparatus, parallel computing method, and recording medium storing parallel computing program |
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| Patent Number: | 10467,184 |
| Publikationsdatum: | November 05, 2019 |
| Appl. No: | 15/994451 |
| Application Filed: | May 31, 2018 |
| Abstract: | A parallel processing apparatus includes: processors; and a network switch, wherein a first processor: generates divided matrix data by dividing the matrix data in such a manner that an overlapping portion is present with each other; transmits the divided matrix data to a second processor; generates first evaluation-value matrix data from the divided matrix data; transmits, to the second processor, first elements in a first overlapping portion of the first evaluation-value matrix data; receives, from the second processor, second elements of a second overlapping portion of second evaluation-value matrix data; calculates first added evaluation data by adding the second elements to the first elements; transmits the first added evaluation data to the second processor; receives, from the second processor, second added evaluation data; and calculates a first C point or a first F point based on the first evaluation-value matrix data which is updated using the second added evaluation data. |
| Inventors: | FUJITSU LIMITED (Kawasaki-shi, Kanagawa, JP) |
| Assignees: | FUJITSU LIMITED (Kawasaki, JP) |
| Claim: | 1. A parallel processing apparatus comprising: a plurality of processors; and a network switch that couples the plurality of processors to each other, wherein a first processor among the plurality of processors: generates divided matrix data, when processing matrix data using a parallel processing based on an algebraic multigrid method and determining a C point or an F point, by dividing the matrix data in such a manner that an overlapping portion is present with each other; transmits the divided matrix data to a second processor which is different from the first processor and is included in the plurality of processors; generates first evaluation-value matrix data from the divided matrix data; transmits, to the second processor, first elements in a first overlapping portion of the first evaluation-value matrix data; receives, from the second processor, second elements of a second overlapping portion of second evaluation-value matrix data which is generated by the second processor; calculates first added evaluation data by adding the second elements to the first elements; transmits the first added evaluation data to the second processor; receives, from the second processor, second added evaluation data which is calculated by the second processor; and calculates a first C point or a first F point based on the first evaluation-value matrix data which is updated by inputting the second added evaluation data to the first evaluation-value matrix data. |
| Claim: | 2. The parallel processing apparatus according to claim 1 , wherein the first processor: transmits information on the first C point or the first F point to the second processor; and receives, from the second processor, information on a second C point or a second F point which is calculated by the second processor. |
| Claim: | 3. The parallel processing apparatus according to claim 2 , wherein the first processor: updates the first C point or the first F point of the first element in the first overlapping portion based on the information on the second C point or the second F point. |
| Claim: | 4. A parallel computing method comprising: generating, by a first processor of a plurality of processors which are coupled by a network switch with each other, divided matrix data, when processing matrix data using a parallel processing based on an algebraic multigrid method and determining a C point or an F point, by dividing the matrix data in such a manner that an overlapping portion is present with each other; transmitting the divided matrix data to a second processor which is different from the first processor and is included in the plurality of processors; generating first evaluation-value matrix data from the divided matrix data; transmitting, to the second processor, first elements in a first overlapping portion of the first evaluation-value matrix data; receiving, from the second processor, second elements of a second overlapping portion of second evaluation-value matrix data which is generated by the second processor; calculating first added evaluation data by adding the second elements to the first elements; transmitting the first added evaluation data to the second processor; receiving, from the second processor, second added evaluation data which is calculated by the second processor; and calculating a first C point or a first F point based on the first evaluation-value matrix data which is updated by inputting the second added evaluation data to the first evaluation-value matrix data. |
| Claim: | 5. The parallel processing apparatus according to claim 4 , further comprising: transmitting, by the first processor, information on the first C point or the first F point to the second processor; and receiving, from the second processor, information on a second C point or a second F point which is calculated by the second processor. |
| Claim: | 6. The parallel processing apparatus according to claim 5 , further comprising: updating the first C point or the first F point of the first element in the first overlapping portion based on the information on the second C point or the second F point. |
| Claim: | 7. A non-transitory computer-readable recording medium storing a parallel computing program which causes a computer to preform a process, the process comprising: generating divided matrix data, when processing matrix data using a parallel processing based on an algebraic multigrid method and determining a C point or an F point, by dividing the matrix data in such a manner that an overlapping portion is present with each other; transmitting the divided matrix data from a first processor to a second processor which is different from the first processor and is included in the plurality of processors; generating first evaluation-value matrix data from the divided matrix data; transmitting, to the second processor, first elements in a first overlapping portion of the first evaluation-value matrix data; receiving, from the second processor, second elements of a second overlapping portion of second evaluation-value matrix data which is generated by the second processor; calculating first added evaluation data by adding the second elements to the first elements; transmitting the first added evaluation data to the second processor; receiving, from the second processor, second added evaluation data which is calculated by the second processor; and calculating a first C point or a first F point based on the first evaluation-value matrix data which is updated by inputting the second added evaluation data to the first evaluation-value matrix data. |
| Claim: | 8. The parallel processing apparatus according to claim 7 , further comprising: transmitting, by the first processor, information on the first C point or the first F point to the second processor; and receiving, from the second processor, information on a second C point or a second F point which is calculated by the second processor. |
| Claim: | 9. The parallel processing apparatus according to claim 8 , further comprising: updating the first C point or the first F point of the first element in the first overlapping portion based on the information on the second C point or the second F point. |
| Patent References Cited: | 7516056 April 2009 Wallis 7-28760 January 1995 |
| Other References: | K. Stüben, “Algebraic Multigrid (AMG): An Introduction with Applications”, GMD-Report 70, pp. 1-127, Nov. 10, 1999, [online], <https://www.scai.fraunhofer.de/content/dan/scai/de/documents/AllgemeineDokumentensammlung/Schnelleoester/SAMG/AMG_Introduction.pdf> (127 pages). cited by applicant David M. Alber et al. “Parallel coarse-grid selection”, Numerical Linear Algebra With Applications, Numer. Linear Algebra Appl. 2007; 14:611-643, Published online Jul. 25, 2007 in Wiley InterScience (33 pages). cited by applicant |
| Primary Examiner: | Mai, Tan V |
| Attorney, Agent or Firm: | Fujitsu Patent Center |
| Dokumentencode: | edspgr.10467184 |
| Datenbank: | USPTO Patent Grants |
| Abstract: | A parallel processing apparatus includes: processors; and a network switch, wherein a first processor: generates divided matrix data by dividing the matrix data in such a manner that an overlapping portion is present with each other; transmits the divided matrix data to a second processor; generates first evaluation-value matrix data from the divided matrix data; transmits, to the second processor, first elements in a first overlapping portion of the first evaluation-value matrix data; receives, from the second processor, second elements of a second overlapping portion of second evaluation-value matrix data; calculates first added evaluation data by adding the second elements to the first elements; transmits the first added evaluation data to the second processor; receives, from the second processor, second added evaluation data; and calculates a first C point or a first F point based on the first evaluation-value matrix data which is updated using the second added evaluation data. |
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