Variable-length coding/decoding device
Gespeichert in:
| Titel: | Variable-length coding/decoding device |
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| Patent Number: | 4,985,700 |
| Publikationsdatum: | January 15, 1991 |
| Appl. No: | 07/313,546 |
| Application Filed: | February 22, 1989 |
| Abstract: | In a variable-length coding/decoding device, an r.multidot.m-bit data word is converted into an r.multidot.n-bit code word, where r is an integer having the relationship 1.ltoreq.r.ltoreq.r.sub.max, a basic data word length consists of a m bits (m is a positive integer), and a basic code word length consists of n bits (n is a positive integer), and each of data words of a variable-length run-length-limited code limiting the run number of bits of a first value (e.g., "o") between successive bits of a second value (e.g., "1") in a binary-coded bit string generated by concatenation of code words after the conversion to a value no smaller than d and no larger than k into a code word corresponding to thereto. At that time, an input data word is once coded into an r.sub.max .multidot.q-bit (q is a positive integer) code word, and then divided into r.sub.max blocks each consisting of q bits, and a code word in each of the blocks is coded to obtain a variable-length run-length-limited code word. Also, the variable-length run-length-limited code word is inverted into a data word corresponding thereto. At that time, the input code word is divided into r.sub.max blocks each consisting of n bits, and a code word in each of the blocks is once decoded into a q-bit (q is a positive integer) code word. Then, the r.sub.max .multidot.q-bit code word is decoded to obtain a data word. |
| Inventors: | Mikami, Fumiyuki (Yokohama, JPX) |
| Assignees: | Canon Kabushiki Kaisha (Tokyo, JPX) |
| Claim: | What is claimed is |
| Claim: | 1. A variable-length coding device for converting an r.multidot.m-bit data word into an r.multidot.n-bit code word, where r is an integer having the relationship 1.ltoreq.r.ltoreq.r.sub.max, a basic data word length consists of m bits (m being a positive integer), and a basic code word length consists of n bits (n being a positive integer), and converting each of the data words of a variable-length run-length-limited code limiting the run number of bits of a first value between successive bits of a second value in a binary-coded bit string generated by concatenation of code words after the conversion to a value no smaller than d and no larger than k (d and k being positive integers), into a code word corresponding thereto, said variable-length coding device comprising |
| Claim: | (A) first coding means for coding an input data word into r.sub.max .multidot.q (q is a positive integer) bits, and outputting a first code word; and |
| Claim: | (B) second coding means for dividing the first code word output from said first coding means into r.sub.max blocks each consisting of q bits, coding a code word in each of the blocks, and outputting a second code word. |
| Claim: | 2. A variable-length coding device according to claim 1, wherein, when there are p (p being a positive integer) kinds of patterns of basic code words having an n-bit basic code word length, said first coding means outputs a code word, each block of which consists of a q-bit (q is a minimum integer satisfying p<2.sup.q) code word corresponding to said p kinds of basic code word patterns, by r.sub.max blocks for the input data word. |
| Claim: | 3. A variable-length coding device according to claim 2, wherein said second coding means includes r.sub.max encoders, each of which receives a respective q-bit code word and each of which outputs an n-bit code word having a basic code word pattern uniquely assigned by the respective q-bit code word. |
| Claim: | 4. A variable-length coding device according to claim 1, wherein said first coding means includes a memory circuit. |
| Claim: | 5. A variable-length coding device according to claim 1, wherein said second coding device includes a memory circuit. |
| Claim: | 6. A variable-length coding device according to claim 1, wherein said second coding means includes gate circuits. |
| Claim: | 7. A variable-length decoding device for converting an r.multidot.m-bit data word into an r.multidot.n-bit code word, where r is an integer having the relationship 1.ltoreq.r.ltoreq.r.sub.max, a basic data word length consists of m bits (m being a positive integer), and a basic code word length consists of n bits (n being a positive integer), and inverting each of the code words of a variable-length run-length-limited code limiting the run number of bits of a first value between successive bits of a second value in a binary-coded bit string generated by concatenation of code words after the conversion to a value no smaller than d and no larger than k (d and k being positive integers), into a data word corresponding thereto, said variable-length decoding device comprising |
| Claim: | (A) first decoding means for dividing an input code word into r.sub.max blocks each consisting of n bits, decoding a code word in each of the blocks into a q-bit (q is a positive integer) code word, and outputting a r.sub.max .multidot.q-bit first code word; and |
| Claim: | (B) second decoding means for decoding the r.sub.max .multidot.q-bit first code word output from said first decoding means, and outputting a second code word. |
| Claim: | 8. A variable-length decoding device according to claim 7, wherein said first decoding means includes r.sub.max decoders, and each of the decoders is arranged so that, when there are p (p is a positive integer) kinds of patterns of basic code words having an n-bit basic code word length, it outputs a code word consisting of q (q is a minimum integer satisfying p<2.sup.q) bits corresponding to said p kinds of basic code word patterns. |
| Claim: | 9. A variable-length decoding device according to claim 8, wherein said second decoding means is arranged so that it outputs an r.sub.max .multidot.n bit code word having a code word pattern uniquely assigned by the r.sub.max .multidot.q-bit code word. |
| Claim: | 10. A variable-length decoding device according to claim 7, wherein said first decoding means includes a memory circuit. |
| Claim: | 11. A variable-length decoding device according to claim 7, wherein said first decoding means includes gate circuits. |
| Claim: | 12. A variable-length decoding device according to claim 7, wherein said second decoding means includes a memory circuit. |
| Current U.S. Class: | 341/59; 341/50; 341/51; 341/58; 341/67 |
| Current International Class: | H03M 700 |
| Patent References Cited: | 4571575 February 1986 McCullough 4593267 June 1986 Kuroda et al. 4641128 February 1987 Schouhamer et al. 4675652 June 1987 Machado 4727421 February 1988 Koga 4760378 July 1988 Iketani et al. 4833470 May 1989 Iketani 4833471 May 1989 Tokuume et al. |
| Primary Examiner: | Shoop, Jr., William M. |
| Assistant Examiner: | Le, Nancy V. |
| Attorney, Agent or Firm: | Fitzpatrick, Cella, Harper & scinto |
| Dokumentencode: | edspgr.04985700 |
| Datenbank: | USPTO Patent Grants |
| Abstract: | In a variable-length coding/decoding device, an r.multidot.m-bit data word is converted into an r.multidot.n-bit code word, where r is an integer having the relationship 1.ltoreq.r.ltoreq.r.sub.max, a basic data word length consists of a m bits (m is a positive integer), and a basic code word length consists of n bits (n is a positive integer), and each of data words of a variable-length run-length-limited code limiting the run number of bits of a first value (e.g., "o") between successive bits of a second value (e.g., "1") in a binary-coded bit string generated by concatenation of code words after the conversion to a value no smaller than d and no larger than k into a code word corresponding to thereto. At that time, an input data word is once coded into an r.sub.max .multidot.q-bit (q is a positive integer) code word, and then divided into r.sub.max blocks each consisting of q bits, and a code word in each of the blocks is coded to obtain a variable-length run-length-limited code word. Also, the variable-length run-length-limited code word is inverted into a data word corresponding thereto. At that time, the input code word is divided into r.sub.max blocks each consisting of n bits, and a code word in each of the blocks is once decoded into a q-bit (q is a positive integer) code word. Then, the r.sub.max .multidot.q-bit code word is decoded to obtain a data word. |
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