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LDPC DECODERS USING FIXED AND ADJUSTABLE PERMUTATORS

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Názov: LDPC DECODERS USING FIXED AND ADJUSTABLE PERMUTATORS
Document Number: 20100107030
Dátum vydania: April 29, 2010
Appl. No: 12/260608
Application Filed: October 29, 2008
Abstrakt: In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices.
Inventors: Graef, Nils (Milpitas, CA, US)
Assignees: AGERE SYSTEMS INC. (Allentown, PA, US)
Claim: 1. An apparatus for decoding a low-density parity-check (LDPC) encoded signal, the apparatus comprising: a plurality of variable node units (VNUs) adapted to generate variable node messages; a plurality of check node units (CNUs) adapted to generate check node messages; and a plurality of paths interconnecting the VNUs and CNUs and adapted to distribute the variable node messages and the check node messages between the VNUs and the CNUs, wherein: the plurality of paths comprises a first path that distributes messages using a combination of cyclic permutation and non-cyclic permutation.
Claim: 2. The apparatus of claim 1, wherein the plurality of paths further comprises a second path that does not use a combination of cyclic permutation and non-cyclic permutation to distribute messages.
Claim: 3. The apparatus of claim 1, wherein the plurality of paths further comprises a second path that distributes messages using a combination of cyclic permutation and non-cyclic permutation, wherein the non-cyclic permutation performed by the second path is different from the non-cyclic permutation performed by the first path.
Claim: 4. The apparatus of claim 1, wherein the cyclic permutation of the first path is performed using an adjustable barrel shifter.
Claim: 5. The apparatus of claim 1, wherein the non-cyclic permutation of the first path is performed using a fixed permutator.
Claim: 6. The apparatus of claim 1, wherein the plurality of paths comprises: a first set of paths that distribute the variable node messages from the VNUs to the CNUs using a first combination of cyclic permutation and non-cyclic permutation; and a second set of paths that distribute the check node messages from the CNUs to the VNUs using a second combination of cyclic permutation and non-cyclic permutation that is opposite of the cyclic permutation and non-cyclic permutation performed by the first combination.
Claim: 7. The apparatus of claim 6, wherein the first set of paths comprises a plurality of different subsets of paths, each different subset of paths comprising a different fixed permutator and an equivalent adjustable barrel shifter.
Claim: 8. The apparatus of claim 7, wherein each different fixed permutator is implemented as a set of connections between (i) a corresponding set of the VNUs and (ii) input ports of the corresponding adjustable barrel shifter.
Claim: 9. The apparatus of claim 1, wherein the apparatus is an integrated circuit.
Claim: 10. The apparatus of claim 1, wherein the apparatus is an LDPC decoder.
Claim: 11. A method for decoding a LDPC encoded signal, the method comprising: (a) generating variable node messages using a plurality of variable node units (VNUs); (b) generating check node messages using a plurality of check node units (CNUs); and (c) distributing the variable node messages and the check node messages between the VNUs and the check node units CNUs using a plurality of paths, wherein: the plurality of paths comprises a first path that distributes messages using a combination of cyclic permutation and non-cyclic permutation.
Claim: 12. The method of claim 11, wherein in step (c), the plurality of paths comprises a second path that does not use a combination of cyclic permutation and non-cyclic permutation to distribute messages.
Claim: 13. The method of claim 11, wherein in step (c), the plurality of paths further comprises as second path that distributes messages using a combination of cyclic permutation and non-cyclic permutation, wherein the non-cyclic permutation performed by the second path is different from the non-cyclic permutation performed by the first path.
Claim: 14. The method of claim 11, wherein the cyclic permutation of the first path is performed using an adjustable barrel shifter.
Claim: 15. The method of claim 11, wherein the non-cyclic permutation of the first path is performed using a fixed permutator.
Claim: 16. The method of claim 11, wherein the plurality of paths comprises: a first set of paths that distribute the variable node messages from the VNUs to the CNUs using a first combination of cyclic permutation and non-cyclic permutation; and a second set of paths that distribute the check node messages from the CNUs to the VNUs using a second combination of cyclic permutation and non-cyclic permutation that is opposite of the cyclic permutation and non-cyclic permutation performed by the first combination.
Claim: 17. The method of claim 16, wherein the first set of paths comprises a plurality of different subsets of paths, each different subset of paths comprising a different fixed permutator and an equivalent adjustable barrel shifter.
Claim: 18. The method of claim 17, wherein each different fixed permutator is implemented as a set of connections between (i) a corresponding set of the VNUs and (ii) input ports of the corresponding adjustable barrel shifter.
Current U.S. Class: 714/752
Current International Class: 03; 06
Prístupové číslo: edspap.20100107030
Databáza: USPTO Patent Applications
Popis
Abstrakt:In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices.