Podrobná bibliografie
| Název: |
EXTRACTION OF A BINARY CODE BASED ON PHYSICAL PARAMETERS OF AN INTEGRATED CIRCUIT |
| Document Number: |
20100097843 |
| Datum vydání: |
April 22, 2010 |
| Appl. No: |
12/641789 |
| Application Filed: |
December 18, 2009 |
| Abstrakt: |
An integrated cell and method for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to make the sign of the difference invariable. |
| Inventors: |
Bardouillet, Michel (Rousset, FR); Rizzo, Pierre (Aix-en-Provence, FR); Malherbe, Alexandre (Trets, FR); Wuidart, Luc (Pourrieres, FR) |
| Assignees: |
STMicroelectronics S.A. (Montrouge, FR) |
| Claim: |
1.-42. (canceled) |
| Claim: |
43. A method for programming a memory cell to store a binary value, the memory cell comprising first and second resistors, the method comprising: reading a sign of a difference between values of the first and second resistors; and decreasing a value of the first resistor or the second resistor to make the sign of the difference invariable. |
| Claim: |
44. The method of claim 43, further comprising reading, as the binary value, said sign of the difference between the values of the first and second resistors. |
| Claim: |
45. The method of claim 43, wherein the decreasing of said value comprises decreasing, in an irreversible and stable manner, within a read operating current range of the memory cell, the value of one of said first and second resistors. |
| Claim: |
46. The method of claim 43, wherein the decreasing of the value is caused by temporarily applying a programming current to a selected resistor of the first and second resistors, the programming current being greater than a current for which the value of the selected resistor is a maximum. |
| Claim: |
47. The method of claim 43, further comprising: prior to decreasing the value, selecting one of the first and second resistors to be a selected resistor based on the sign of the difference. |
| Claim: |
48. The method of claim 47, wherein the decreasing of said value comprises: increasing step-by-step the current in the selected resistor; and measuring the value of the selected resistor as the current in the selected resistor is increased. |
| Claim: |
49. The method of claim 47, wherein the decreasing of said value comprises: determining a programming current using a predetermined table of correspondence between resistor stabilization current and a desired final resistance and supplying the programming current to the selected resistor. |
| Claim: |
50. The method of claim 43, wherein the first and second resistors are manufactured to be substantially identical. |
| Claim: |
51. An integrated memory cell for extracting a binary value based on a difference between two resistor values, comprising: a first circuit configured to read a sign of the difference between said two resistor values; and a second circuit configured to decrease a value of one of said resistors to make said sign of the difference invariable. |
| Claim: |
52. The cell of claim 51, wherein the first circuit is configured to read the sign of the difference as a binary value. |
| Claim: |
53. The cell of claim 51, wherein the decreasing of said value comprises decreasing, in an irreversible and stable manner, within the read operating current range of the cell, the value of one of said resistors. |
| Claim: |
54. The cell of claim 51, wherein the resistors are made of polysilicon and are sized to have identical nominal values. |
| Claim: |
55. The cell of claim 53, wherein the value decrease is caused by temporarily applying, in the corresponding resistor, a current which is greater than the current for which the value of the resistor is maximum. |
| Claim: |
56. The cell of claim 51, applied to the extraction of the binary value based on a propagation of an edge of a triggering signal in two electric paths, comprising, between two voltage supply terminals, two parallel branches each comprising, in series: one of said resistors for differentiating the electric paths; a read transistor, the junction point of the resistor and the read transistor of each branch defining an output terminal of the cell, and the gate of the read transistor of each branch being connected to the output terminal of the other branch; and a selection transistor. |
| Claim: |
57. The cell of claim 56, wherein each branch further comprises a stabilization transistor connecting its output terminal to said terminal of application of a voltage opposite to that to which the resistor of the involved branch is connected. |
| Claim: |
58. The cell of claim 57, wherein the decreasing of said value comprises decreasing, in an irreversible and stable manner, within the read operating current range of the cell, the value of one of said resistors, and wherein the stabilization transistors are used to cause said decrease in the value of one of the resistors. |
| Claim: |
59. The cell of claim 56, wherein said voltage supply is chosen from a relatively low read voltage and a relatively high voltage of stabilization of the initial cell state. |
| Claim: |
60. The cell of claim 51, comprising: two parallel branches each comprising one of said resistors connected between a first supply terminal and a terminal for differentially reading the cell state; and at least one programming switch connecting one of said read terminals to a second terminal of application of the supply voltage. |
| Claim: |
61. The cell of claim 60, wherein each branch comprises a programming switch. |
| Current U.S. Class: |
365/148 |
| Current International Class: |
11; 11 |
| Přístupové číslo: |
edspap.20100097843 |
| Databáze: |
USPTO Patent Applications |