Bibliographische Detailangaben
| Titel: |
EFFICIENT CHECK NODE MESSAGE TRANSFORM APPROXIMATION FOR LDPC DECODER |
| Document Number: |
20090177869 |
| Publikationsdatum: |
July 9, 2009 |
| Appl. No: |
12/348674 |
| Application Filed: |
January 05, 2009 |
| Abstract: |
In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp functions is described which involves using a simple bit mapping between fixed point fractional data format and floating point format. The method avoids costly lookup tables and complex computations and further reduces the core processing to a sequence of additions and subtractions using alternating fixed point and floating point processing units. The method is well suited for use in highly optimized hardware implementations which can take advantage of modern advances in standard floating point arithmetic circuit design as well as for software implementation on a wide class of processors equipped with FPU where the invention avoids the need for a typical multi-cycle series of log/exp instructions and especially on a SIMD FPU-equipped processors where log/exp functions are typically scalar. |
| Inventors: |
Novichkov, Vladimir (Towaco, NJ, US); Richardson, Tom (South Orange, NJ, US) |
| Assignees: |
QUALCOMM Incorporated (San Diego, CA, US) |
| Claim: |
1. A decoder having: a memory for receiving and storing an input value having an integer part and a fractional part; and a floating point processor connected with the memory and configured to receive a floating point number having an exponent value mapped from the integer part and a significand value mapped from the fractional part wherein the floating point number approximates the logarithm of the input value. |
| Claim: |
2. The decoder of claim 1 wherein the decoder is a low density parity check decoder. |
| Claim: |
3. The decoder of claim 1 wherein the decoder is a turbo-convolutional decoder. |
| Claim: |
4. The decoder of claim 1 wherein the logarithm is a base ten logarithm. |
| Claim: |
5. The decoder of claim 1 wherein the logarithm is a base two logarithm. |
| Claim: |
6. The decoder of claim 1 wherein the floating point processor is configured to generate an output value, the output value having an exponent value mappable to an ouptut integer part and a fractional part mappable to an output fractional part wherein the output integer part and fractional part approximate the exponential of the output value. |
| Claim: |
7. A decoder having: means for receiving and storing an input value having an integer part and a fractional part; and means for mapping the integer part to to an exponent value and for mapping the fractional part to the significand value to form a floating point number wherein the floating point number approximates the logarithm of the input value. |
| Claim: |
8. The decoder of claim 7 wherein the decoder is a low density parity check decoder and the mapping means is configured to perform a bit-wise inversion operation. |
| Claim: |
9. The decoder of claim 7 wherein the decoder is a turbo-convolutional decoder. |
| Claim: |
10. The decoder of claim 7 further comprising a means for generating an output value the output value having an exponent value mappable to an ouptut integer part and an output fractional part mappable to an output fractional part wherein the output integer art and output fractional part approximate the exponential of the output value. |
| Claim: |
11. A method for approximating a logarithm, the method comprising: receiving and storing an input value having an integer part and a fractional part; and mapping the integer part to an exponent value in a floating point processor and mapping the fractional part to a significand value in the floating point processor forming a floating point number that approximates the logarithm of the input value. |
| Claim: |
12. The method of claim 11 wherein the mapping is done in a low density parity check decoder. |
| Claim: |
13. The decoder of claim 11 wherein the decoder is done in a turbo-convolutional decoder. |
| Claim: |
14. The decoder of claim 11 wherein the logarithm is a base ten logarithm. |
| Claim: |
15. The decoder of claim 11 wherein the logarithm is a base two logarithm. |
| Claim: |
16. A computer program product embedded on a computer readable medium, the computer program product having: instructions for receiving and storing an input value in memory, the input value having an integer part and a fractional part; and instructions for mapping the integer part to an exponent value in a floating point processor and for mapping the fractional part to a significand value in the floating point processor forming a floating point number that approximates the logarithm of the input value. |
| Claim: |
17. The method of claim 16 wherein the mapping is done in a low density parity check decoder. |
| Claim: |
18. The decoder of claim 16 wherein the decoder is done in a turbo-convolutional decoder. |
| Claim: |
19. The decoder of claim 16 wherein the logarithm is a base ten logarithm. |
| Claim: |
20. The decoder of claim 16 wherein the logarithm is a base two logarithm. |
| Current U.S. Class: |
712/222 |
| Current International Class: |
06; 03; 06 |
| Dokumentencode: |
edspap.20090177869 |
| Datenbank: |
USPTO Patent Applications |