Bibliographische Detailangaben
| Titel: |
Efficient check node message transform approximation for LDPC decoder |
| Document Number: |
20060236195 |
| Publikationsdatum: |
October 19, 2006 |
| Appl. No: |
11/082405 |
| Application Filed: |
March 17, 2005 |
| Abstract: |
In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp functions is described which involves using a simple bit mapping between fixed point fractional data format and floating point format. The method avoids costly lookup tables and complex computations and further reduces the core processing to a sequence of additions and subtractions using alternating fixed point and floating point processing units. The method is well suited for use in highly optimized hardware implementations which can take advantage of modern advances in standard floating point arithmetic circuit design as well as for software implementation on a wide class of processors equipped with FPU where the invention avoids the need for a typical multi-cycle series of log/exp instructions and especially on a SIMD FPU-equipped processors where log/exp functions are typically scalar. |
| Inventors: |
Novichkov, Vladimir (Towaco, NJ, US); Richardson, Tom (South Orange, NJ, US) |
| Claim: |
1. A method of processing a set of binary values using at least one floating point processing module, the method comprising: generating a set of floating point processing module input bits from a value represented in a fixed point fractional format, each individual bit of at least a portion of said value determining a bit value of a corresponding individual bit in said set of floating point processing module input bits; operating the floating point processing module to perform at least one floating point processing computation using said generated set of floating point processing module input bits as an input to the at least one floating point computation, said floating point computation module producing from the processing of said set of floating point processing module input bits a second set of bits arranged in a floating point format; generating a set of fixed point processing module input bits from the second set of bits arranged in a floating point format; and operating the fixed point processing module to perform at least one fixed point processing computation using said generated set of fixed point processing module input bits. |
| Claim: |
2. The method of claim 1, wherein the portion of said value includes multiple bits, said multiple bits including at least 50% of the bits in said value. |
| Claim: |
3. The method of claim 1, wherein the portion of said value includes at least 70% of the bits in said value, wherein said value includes at least 32 bits, and wherein said portion of said value includes at least 31 bits. |
| Claim: |
4. The method of claim 1, wherein the portion of said value includes at least two bits corresponding to an integer portion of said value and at least three bits corresponding to a fraction portion of said value, said portion including at least said two and three bits. |
| Claim: |
5. The method of claim 1, wherein said step of generating a set of floating point processing module input bits includes reading the value from a first storage device. |
| Claim: |
6. The method of claim 5, wherein each floating point processing module input bit value which is generated from a corresponding stored bit value has the same value as the stored bit value to which the generated bit value corresponds; and wherein generating a set of fixed point processing module input bits from the second set of bits arranged in a floating point format includes reading at least a portion of the second set of bits arranged in a floating point format from memory, said portion of the second set of bits including multiple bits, each of the multiple bits determining the value of a corresponding single one of the fired point processing module input bits, each corresponding single one of the fixed point processing module input bits having the same value as the bit from the second set of bits to which it corresponds. |
| Claim: |
7. The method of claim 5, wherein said step of generating a set of floating point processing module input bits further includes: including in said generated set of floating point processing module input bits, at least one padding bit value having a predetermined constant value, said at least one padding bit value being in addition to input bits values determined from corresponding bit values of said read stored value. |
| Claim: |
8. The method of claim 5, wherein said step of generating a set of floating point processing module input bits further includes: performing a bitwise inversion operation on at least some bits read from memory to determine the value of corresponding individual bits in said generated set of floating point processing module input bits. |
| Claim: |
9. The method of claim 8, wherein the step of generating a set of fixed point processing module input bits from the second set of bits arranged in a floating point format includes performing a bitwise inversion operation on at least a plurality of bits included in said second set of bits to produce a corresponding plurality of fixed point processing module input bits. |
| Claim: |
10. The method of claim 5, wherein said at least one floating point processing operation is one of a floating point addition operation in which case said floating point processing module includes a floating point adder and said at least one floating point processing operation is a floating point subtraction in which case the floating point processing module includes at least one floating point subtractor. |
| Claim: |
11. The method of claim 10, wherein said floating point processing module includes both a floating point adder and a floating point subtractor. |
| Claim: |
12. The method of claim 1, further comprising: storing a resulting fixed point value generated by operating the fixed point processing module to perform at least one fixed point processing computation; generating a second set of floating point processing module input bits from the stored resulting fixed point value, each individual bit of at least a portion of said stored resulting fixed point value determining a bit value of a corresponding individual bit in said second set of floating point processing module input bits; performing at least one floating point processing computation using said generated second set of floating point processing module input bits as an input to the at least one floating point computation thereby producing from the processing of said second set of floating point processing module input bits an additional set of bits arranged in a floating point format. |
| Claim: |
13. The method of claim 12, further comprising: generating another set of fixed point processing module input bits from the additional set of bits arranged in a floating point format by generating a plurality of bit values from a corresponding plurality of bit values in said additional set of bits with each bit being generated on a one to one basis from the corresponding bit in the additional set of bit values. |
| Claim: |
14. The method of claim 1, where said method is a method of implementing a low density party check decoding operation, wherein said stored value is a parity check message; and wherein said floating point processing module includes an accumulator for storing a sum represented in floating point format that is generated by a floating point addition operation which used said set of floating point processing module input bits as an input to said floating point addition operation. |
| Claim: |
15. The method of claim 14, wherein said floating point processing module further includes a subtractor; and wherein said second set of bits arranged in a floating point format is generated by said floating point processing module performing a floating point subtraction operation including subtracting a floating point value generated from said set of floating point processing module input bits, from a value generated from the stored sum. |
| Claim: |
16. A system for processing a set of binary values, the system comprising: means for generating a set of floating point processing module input bits from a stored value represented in a fixed point fractional format, each individual bit of at least a portion of said stored value determining a bit value of a corresponding individual bit in said set of floating point processing module input bits; a floating point processing module for performing at least one floating point processing computation using said generated set of floating point processing module input bits as an input to the at least one floating point computation, said floating point computation module producing from the processing of said set of floating point processing module input bits a second set of bits arranged in a floating point format; means for generating a set of fixed point processing module input bits from the second set of bits arranged in a floating point format; and a fixed point processing module for perform at least one fixed point processing computation using said generated set of fixed point processing module input bits. |
| Claim: |
17. The system of claim 16, wherein the portion of said stored value includes at least two bits corresponding to an integer portion of said stored value and at least three bits corresponding to a fraction portion of said stored value, said portion including at least said two and three bits. |
| Claim: |
18. The system of claim 16, wherein said means for generating a set of floating point processing module input bits includes a bit inverter. |
| Claim: |
19. The system of claim 18, wherein said means for generating a set of fixed point processing module input bits includes a bit inverter. |
| Claim: |
20. The system of claim 16, wherein said means for generating a set of floating point processing module input bits includes means for reading the stored value from a first storage device. |
| Claim: |
21. The method of claim 16, wherein each floating point processing module input bit value which is generated from a corresponding stored bit value has the same value as the stored bit value to which the generated bit value corresponds; and wherein generating a set of fixed point processing module input bits from the second set of bits arranged in a floating point format includes reading at least a portion of the second set of bits arranged in a floating point format from memory, said portion of the second set of bits including multiple bits, each of the multiple bits determining the value of a corresponding single one of the fired point processing module input bits, each corresponding single one of the fixed point processing module input bits having the same value as the bit from the second set of bits to which it corresponds. |
| Claim: |
22. A method of processing a set of binary values using at least one fixed point processing module, the method comprising: generating a set of fixed point processing module input bits from a stored value represented in a floating point format, each individual bit of at least a portion of said stored value determining a bit value of a corresponding individual bit in said set of fixed point processing module input bits; operating the fixed point processing module to perform at least one fixed point processing computation using said generated set of fixed point processing module input bits as an input to the at least one fixed point computation, said fixed point computation producing from the processing of said set of fixed point processing module input bits a second set of bits arranged in a fixed point fractional format; generating a set of floating point processing module input bits from the second set of bits arranged in a fixed point fractional format; and operating the floating point processing module to perform at least one floating point processing computation using said generated set of floating point processing module input bits. |
| Claim: |
23. The method of claim 22, wherein said step of generating a set of fixed point processing module input bits includes reading the stored value from a first storage device. |
| Claim: |
24. The method of claim 23, wherein each fixed point processing module input bit value which is generated from a corresponding stored bit value has the same value as the stored bit value to which the generated bit value corresponds; and wherein generating a set of floating point processing module input bits from the second set of bits arranged in a fixed point format includes reading at least a portion of the second set of bits arranged in a fixed point format from memory, said portion of the second set of bits including multiple bits, each of the multiple bits determining the value of a corresponding single one of the floating point processing module input bits, each corresponding single one of the floating point processing module input bits having the same value as the bit from the second set of bits to which it corresponds. |
| Claim: |
25. The method of claim 23, wherein said step of generating a set of floating point processing module input bits further includes: including in said generated set of floating point processing module input bits, at least one padding bit value having a predetermined constant value, said at least one padding bit value being in addition to input bits values determined from corresponding bit values of said read stored value. |
| Claim: |
26. The method of claim 23, wherein said step of generating a set of fixed point processing module input bits further includes: performing a bitwise inversion operation on at least some bits read from memory to determine the value of corresponding individual bits in said generated set of fixed point processing module input bits. |
| Claim: |
27. The method of claim 26, wherein the step of generating a set of floating point processing module input bits from the second set of bits arranged in a fixed point format includes performing a bitwise inversion operation on at least a plurality of bits included in said second set of bits to produce a corresponding plurality of floating point processing module input bits. |
| Claim: |
28. A system for processing a set of binary values using at least one fixed point processing module, the method comprising: means for generating a set of fixed point processing module input bits from a stored value represented in a floating point format, each individual bit of at least a portion of said stored value determining a bit value of a corresponding individual bit in said set of fixed point processing module input bits; a fixed point processing module for performing at least one fixed point processing computation using said generated set of fixed point processing module input bits as an input to at least one fixed point computation, said fixed point computation producing from the processing of said set of fixed point processing module input bits a second set of bits arranged in a fixed point fractional format; means for generating a set of floating point processing module input bits from the second set of bits arranged in a fixed point fractional format; and a floating point processing module to perform at least one floating point processing computation using said generated set of floating point processing module input bits. |
| Claim: |
29. The system of claim 28, wherein said means for generating a set of fixed point processing module input bits includes circuitry for reading the stored value from a first storage device. |
| Claim: |
30. The system of claim 29, wherein each fixed point processing module input bit value which is generated from a corresponding stored bit value has the same value as the stored bit value to which the generated bit value corresponds; and wherein said means generating a set of floating point processing module input bits from the second set of bits arranged in a fixed point format includes means for reading at least a portion of the second set of bits arranged in a fixed point format from memory, said portion of the second set of bits including multiple bits, each of the multiple bits determining the value of a corresponding single one of the floating point processing module input bits, each corresponding single one of the floating point processing module input bits having the same value as the bit from the second set of bits to which it corresponds. |
| Claim: |
31. The system of claim 28, wherein said means for generating a set of floating point processing module input bits further includes: a padding circuit for including in said generated set of floating point processing module input bits, at least one padding bit value having a predetermined constant value, said at least one padding bit value being in addition to input bits values determined from corresponding bit values of said read stored value. |
| Claim: |
32. The system of claim 28, wherein said means for generating a set of fixed point processing module input bits further includes: a bitwise inverter module for performing a bitwise inversion operation on at least some bits read from memory to determine the value of corresponding individual bits in said generated set of fixed point processing module input bits. |
| Claim: |
33. The method of claim 1 wherein said step of generating a set of floating point processing module input bits performs an approximation for an exp computational operation. |
| Claim: |
34. The method of claim 1 wherein said step of generating a set of fixed point processing module input bits from the second set of bits arranged in a floating point format performs an approximation for a log computational operation. |
| Claim: |
35. The system of claim 28 wherein said means for generating a set of fixed point processing module input bits from a stored value represented in a floating point format performs an approximation of an log computational operation. |
| Claim: |
36. The system of claim 28 wherein said means for generating a set of floating point processing module input bits from the second set of bits arranged in a fixed point fractional format performs an approximation of an exp computational operation. |
| Claim: |
37. The system of claim 32, wherein said means for generating a set of fixed point processing module input bits from a stored value represented in a floating point format and said means for generating a set of floating point processing module input bits from the second set of bits arranged in a fixed point fractional format is part of an LPDC decoder. |
| Current U.S. Class: |
714758/000 |
| Current International Class: |
03 |
| Dokumentencode: |
edspap.20060236195 |
| Datenbank: |
USPTO Patent Applications |