A hardware peripheral for Java bytecodes translation acceleration
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| Title: | A hardware peripheral for Java bytecodes translation acceleration |
|---|---|
| Authors: | Sideris, I, Moshopoulos, N, Pekmestzi, K |
| Publication Year: | 2010 |
| Collection: | National Technical University of Athens (NTUA): DSpace |
| Subject Terms: | ASIC, Java processor, RISC, stack folding, ASIC technologies, Hard task, Hardware acceleration units, Java bytecodes, Java processors, Java program, Just-in-time compilation, Speed-ups, Electric power supplies to apparatus, Embedded systems, Java programming language, Just in time production, Nanotechnology, Reduced instruction set computing, Computer software |
| Document Type: | other/unknown material |
| Language: | unknown |
| Relation: | 552; 553 |
| DOI: | 10.1145/1774088.1774201 |
| Availability: | https://doi.org/10.1145/1774088.1774201 |
| Accession Number: | edsbas.F73B8B6B |
| Database: | BASE |
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