A hardware peripheral for Java bytecodes translation acceleration
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| Titel: | A hardware peripheral for Java bytecodes translation acceleration |
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| Autoren: | Sideris, I, Moshopoulos, N, Pekmestzi, K |
| Publikationsjahr: | 2010 |
| Bestand: | National Technical University of Athens (NTUA): DSpace |
| Schlagwörter: | ASIC, Java processor, RISC, stack folding, ASIC technologies, Hard task, Hardware acceleration units, Java bytecodes, Java processors, Java program, Just-in-time compilation, Speed-ups, Electric power supplies to apparatus, Embedded systems, Java programming language, Just in time production, Nanotechnology, Reduced instruction set computing, Computer software |
| Publikationsart: | other/unknown material |
| Sprache: | unknown |
| Relation: | https://dspace.lib.ntua.gr/xmlui/handle/123456789/32746; 552; 553 |
| DOI: | 10.1145/1774088.1774201 |
| Verfügbarkeit: | https://dspace.lib.ntua.gr/xmlui/handle/123456789/32746 https://doi.org/10.1145/1774088.1774201 |
| Dokumentencode: | edsbas.F73B8B6B |
| Datenbank: | BASE |
Nájsť tento článok vo Web of Science | DOI: | 10.1145/1774088.1774201 |
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