Podrobná bibliografie
| Název: |
An instruction set extension for java bytecodes translation acceleration |
| Autoři: |
Sideris, I, Pekmestzi, K, Economakos, G |
| Rok vydání: |
2008 |
| Sbírka: |
National Technical University of Athens (NTUA): DSpace |
| Témata: |
Embedded Processor, High Performance, Instruction Set Extension, java bytecode, Java Programming, First Order, Just In Time, Application specific integrated circuits, Computer architecture, Computer programming languages, Embedded systems, Program translators, Translation (languages), Applications, First orders, High performance embedded processors, Instruction Set Extensions, Java byte codes, Just in times, RISC processors, Speed-up, Super scalars, Synthesis tools, Java programming language |
| Druh dokumentu: |
other/unknown material |
| Jazyk: |
unknown |
| Relation: |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/32156; 116; 123 |
| DOI: |
10.1109/ICSAMOS.2008.4664854 |
| Dostupnost: |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/32156
https://doi.org/10.1109/ICSAMOS.2008.4664854 |
| Přístupové číslo: |
edsbas.EAADC698 |
| Databáze: |
BASE |
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