Bibliographic Details
| Title: |
An instruction set extension for java bytecodes translation acceleration |
| Authors: |
Sideris, I, Pekmestzi, K, Economakos, G |
| Publication Year: |
2008 |
| Collection: |
National Technical University of Athens (NTUA): DSpace |
| Subject Terms: |
Embedded Processor, High Performance, Instruction Set Extension, java bytecode, Java Programming, First Order, Just In Time, Application specific integrated circuits, Computer architecture, Computer programming languages, Embedded systems, Program translators, Translation (languages), Applications, First orders, High performance embedded processors, Instruction Set Extensions, Java byte codes, Just in times, RISC processors, Speed-up, Super scalars, Synthesis tools, Java programming language |
| Document Type: |
other/unknown material |
| Language: |
unknown |
| Relation: |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/32156; 116; 123 |
| DOI: |
10.1109/ICSAMOS.2008.4664854 |
| Availability: |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/32156
https://doi.org/10.1109/ICSAMOS.2008.4664854 |
| Accession Number: |
edsbas.EAADC698 |
| Database: |
BASE |
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