Archives, T. P. S. U. C. Reordering Algorithm for Minimizing Test Power in VLSI Circuits. http://www.engineeringletters.com/issues_v14/issue_1/EL_14_1_15.pdf.
Chicago Style (17th ed.) CitationArchives, The Pennsylvania State University CiteSeerX. "Reordering Algorithm for Minimizing Test Power in VLSI Circuits." Http://www.engineeringletters.com/issues_v14/issue_1/EL_14_1_15.pdf .
MLA (9th ed.) CitationArchives, The Pennsylvania State University CiteSeerX. "Reordering Algorithm for Minimizing Test Power in VLSI Circuits." Http://www.engineeringletters.com/issues_v14/issue_1/EL_14_1_15.pdf, .
Warning: These citations may not always be 100% accurate.