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Reordering Algorithm for Minimizing Test Power in VLSI Circuits

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Bibliographic Details
Title: Reordering Algorithm for Minimizing Test Power in VLSI Circuits
Contributors: The Pennsylvania State University CiteSeerX Archives
Source: http://www.engineeringletters.com/issues_v14/issue_1/EL_14_1_15.pdf.
Collection: CiteSeerX
Subject Terms: Index Terms — ATPG, Hamming Distance, Power Consumption, Reordering Algorithm, Switching Activity
Description: — Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel method which aims at minimizing the total power consumption during testing. This is achieved by minimizing the switching activity in the circuit by reducing the Hamming Distance between successive test vectors. In this method the test vectors are reordered for minimum total hamming distance and the same vector set is used for testing. Experimental results with ISCAS benchmark circuits show that the switching activity can be reduced up to 21 % in comparison with conventional ATPG Algorithms like DEFGEN. The Switching activity is reduced significantly when compared with existing methods.
Document Type: text
File Description: application/pdf
Language: English
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.148.7604; http://www.engineeringletters.com/issues_v14/issue_1/EL_14_1_15.pdf
Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.148.7604
http://www.engineeringletters.com/issues_v14/issue_1/EL_14_1_15.pdf
Rights: Metadata may be used without restrictions as long as the oai identifier remains attached to it.
Accession Number: edsbas.E5C5CE14
Database: BASE
Description
Abstract:— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel method which aims at minimizing the total power consumption during testing. This is achieved by minimizing the switching activity in the circuit by reducing the Hamming Distance between successive test vectors. In this method the test vectors are reordered for minimum total hamming distance and the same vector set is used for testing. Experimental results with ISCAS benchmark circuits show that the switching activity can be reduced up to 21 % in comparison with conventional ATPG Algorithms like DEFGEN. The Switching activity is reduced significantly when compared with existing methods.