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Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes

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Title: Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes
Authors: Mahdavi, Mojtaba, Liu, Liang, Edfors, Ove, Lentmaier, Michael, Wehn, Norbert, Weithoffer, Stefan
Contributors: Skane University Hospital Lund, Department of Electrical and Information Technology (EIT), Technische Universität Kaiserslautern (TU Kaiserslautern), Microelectronic Systems Design Research Group, University of Kaiserslautern, Equipe Algorithm Architecture Interactions (Lab-STICC_2AI), Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom Paris (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom Paris (IMT)-École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom Paris (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom Paris (IMT), Département Mathematical and Electrical Engineering (IMT Atlantique - MEE), IMT Atlantique (IMT Atlantique), Institut Mines-Télécom Paris (IMT)-Institut Mines-Télécom Paris (IMT), ANR-20-CE25-0007,TurboLEAP,Turbo décodage parallèle pour la montée en débit à consommation et surface réduites(2020)
Source: ISTC 2021: 11th International Symposium on Topics in Coding ; https://imt-atlantique.hal.science/hal-03280057 ; ISTC 2021: 11th International Symposium on Topics in Coding, Aug 2021, Montréal, Canada. ⟨10.1109/ISTC49272.2021.9594185⟩
Publisher Information: CCSD
Publication Year: 2021
Collection: Université de Bretagne Occidentale: HAL
Subject Terms: [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Subject Geographic: Montréal
Time: Montréal, Canada
Description: International audience ; Having close-to-capacity performance and low error floor, even for small block lengths, make spatially coupled serially concatenated codes (SC-SCCs) a very promising class of codes. However, classical window decoding of SC-SCCs either limits the minimum block length or requires a large number of iterations, which increases the complexity and constrains the degree to which an SC-SCC decoder architecture can be parallelized. In this paper we propose jumping window decoding (JWD), an algorithmic modification to the scheduling of decoding such that it enables pipelined implementation of SC-SCCs decoder. Also, it provides flexibility in terms of block length and number of iterations and makes them independent of each other. Simulation results show that our scheme outperforms classical window decoding of both SC-SCCs and uncoupled SCCs, in terms of performance. Furthermore, we present a fully pipelined hardware architecture to realize JWD of SC-SCCs along with area estimates in 12nm technology for the respective case study.
Document Type: conference object
Language: English
DOI: 10.1109/ISTC49272.2021.9594185
Availability: https://imt-atlantique.hal.science/hal-03280057
https://imt-atlantique.hal.science/hal-03280057v1/document
https://imt-atlantique.hal.science/hal-03280057v1/file/ISTC_2021.pdf
https://doi.org/10.1109/ISTC49272.2021.9594185
Rights: info:eu-repo/semantics/OpenAccess
Accession Number: edsbas.D4AF1F2A
Database: BASE
Description
Abstract:International audience ; Having close-to-capacity performance and low error floor, even for small block lengths, make spatially coupled serially concatenated codes (SC-SCCs) a very promising class of codes. However, classical window decoding of SC-SCCs either limits the minimum block length or requires a large number of iterations, which increases the complexity and constrains the degree to which an SC-SCC decoder architecture can be parallelized. In this paper we propose jumping window decoding (JWD), an algorithmic modification to the scheduling of decoding such that it enables pipelined implementation of SC-SCCs decoder. Also, it provides flexibility in terms of block length and number of iterations and makes them independent of each other. Simulation results show that our scheme outperforms classical window decoding of both SC-SCCs and uncoupled SCCs, in terms of performance. Furthermore, we present a fully pipelined hardware architecture to realize JWD of SC-SCCs along with area estimates in 12nm technology for the respective case study.
DOI:10.1109/ISTC49272.2021.9594185