An efficient parallel biconnectivity algorithm
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| Title: | An efficient parallel biconnectivity algorithm |
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| Authors: | Robert E. Tarjan |
| Contributors: | The Pennsylvania State University CiteSeerX Archives |
| Source: | http://www.umiacs.umd.edu/users/vishkin/TEACHING/ENEE759KS12/TV85.pdf. |
| Publication Year: | 1985 |
| Collection: | CiteSeerX |
| Subject Terms: | Key words, parallel graph algorithm, biconnected components, blocks |
| Description: | In this paper we propose a new algorithm for finding the blocks (biconnected components) of an undirected graph. A serial implementation runs in O(n + m) time and space on a graph of n vertices and m edges. A parallel implementation runs in O(log n) time and O(n + m) space using O(n + m) processors on a concurrent-read, concurrent-write parallel RAM. An alternative implementation runs in O(n2/p) time and O(n2) space using any number p < = n/log n of processors, on a concurrent-read, exclusive-write parallel RAM. The last algorithm has optimal speedup, assuming an adjacency matrix representation of the input. A general algorithmic technique that simplifies and improves computation of various functions on trees is introduced. This technique typically requires O(log n) time using processors and O(n) space on an exclusive-read exclusive-write parallel RAM. |
| Document Type: | text |
| File Description: | application/pdf |
| Language: | English |
| Relation: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.465.8898; http://www.umiacs.umd.edu/users/vishkin/TEACHING/ENEE759KS12/TV85.pdf |
| Availability: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.465.8898 http://www.umiacs.umd.edu/users/vishkin/TEACHING/ENEE759KS12/TV85.pdf |
| Rights: | Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| Accession Number: | edsbas.CAD08B9 |
| Database: | BASE |
Nájsť tento článok vo Web of Science | Abstract: | In this paper we propose a new algorithm for finding the blocks (biconnected components) of an undirected graph. A serial implementation runs in O(n + m) time and space on a graph of n vertices and m edges. A parallel implementation runs in O(log n) time and O(n + m) space using O(n + m) processors on a concurrent-read, concurrent-write parallel RAM. An alternative implementation runs in O(n2/p) time and O(n2) space using any number p < = n/log n of processors, on a concurrent-read, exclusive-write parallel RAM. The last algorithm has optimal speedup, assuming an adjacency matrix representation of the input. A general algorithmic technique that simplifies and improves computation of various functions on trees is introduced. This technique typically requires O(log n) time using processors and O(n) space on an exclusive-read exclusive-write parallel RAM. |
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