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Computer Systems Architecture at Yale. The Enormous Longword Instruction (ELI) Machine Progress and Research Plans.

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Bibliographic Details
Title: Computer Systems Architecture at Yale. The Enormous Longword Instruction (ELI) Machine Progress and Research Plans.
Authors: Fisher,Joseph A
Contributors: YALE UNIV NEW HAVEN CT DEPT OF COMPUTER SCIENCE
Source: DTIC AND NTIS
Publication Year: 1982
Collection: Defense Technical Information Center: DTIC Technical Reports database
Subject Terms: Computer Programming and Software, Computer Hardware, COMPUTER ARCHITECTURE, COMPUTER AIDED INSTRUCTION, COMPILERS, MICROPROCESSORS, STATE OF THE ART, PARALLEL PROCESSORS, SCHEDULING, CENTRAL PROCESSING UNITS, MACHINE CODING, HIGH LEVEL LANGUAGES, ELI(Enormous Longword Instruction), VLSI(Very Large Scale Integration)
Description: The overall goal of the Yale Computer Science Department's Attached Processor Project systems group is to improve dramatically the practical state of the art in CPU-bound scientific computing. Specifically, we are building a very long (probably over 500 bits) instruction word machine, the ELI-512. A machine with this much irregular parallelism can reasonably be coded only in high-level languages; this requires state-of-the-art techniques in compiling horizontal microcode. An effective approach to this problem, trace scheduling, has been developed at Yale over the past three years. Longword instruction machines are now quite popular and may offer the best alternative for obtaining supercomputer power at a fraction of its current cost. Unfortunately, they are already being built too wide for people or today's compilers to generate significant quantities of good code for them. Without this or similar work, there is little chance that more usable wide-word architectures will be commercially developed. It is an aim of this project to cause such commercial development to occur. The following are key steps in building the ELI-512: (1) Parallelism measurements, (2) Compiling for existing machines, (3) Compiling for, designing, and building the highly parallel ELI-512, (4) Allowing the compiler to design highly parallel customized procesors. ; Sponsored in part by Grants NSD-MCS81-06181 and NSF-MCS81-0746.
Document Type: text
File Description: text/html
Language: English
Relation: http://www.dtic.mil/docs/citations/ADA121569
Availability: http://www.dtic.mil/docs/citations/ADA121569
http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=ADA121569
Rights: APPROVED FOR PUBLIC RELEASE
Accession Number: edsbas.C8C0893A
Database: BASE
Description
Abstract:The overall goal of the Yale Computer Science Department's Attached Processor Project systems group is to improve dramatically the practical state of the art in CPU-bound scientific computing. Specifically, we are building a very long (probably over 500 bits) instruction word machine, the ELI-512. A machine with this much irregular parallelism can reasonably be coded only in high-level languages; this requires state-of-the-art techniques in compiling horizontal microcode. An effective approach to this problem, trace scheduling, has been developed at Yale over the past three years. Longword instruction machines are now quite popular and may offer the best alternative for obtaining supercomputer power at a fraction of its current cost. Unfortunately, they are already being built too wide for people or today's compilers to generate significant quantities of good code for them. Without this or similar work, there is little chance that more usable wide-word architectures will be commercially developed. It is an aim of this project to cause such commercial development to occur. The following are key steps in building the ELI-512: (1) Parallelism measurements, (2) Compiling for existing machines, (3) Compiling for, designing, and building the highly parallel ELI-512, (4) Allowing the compiler to design highly parallel customized procesors. ; Sponsored in part by Grants NSD-MCS81-06181 and NSF-MCS81-0746.