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Analysis of Minimal LDPC Decoder System on a Chip Implementation

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Title: Analysis of Minimal LDPC Decoder System on a Chip Implementation
Authors: Palenik, Tomas, Farkas, Peter, Rakus, Martin, Dobos, Jan
Publisher Information: Společnost pro radioelektronické inženýrství
Publication Year: 2015
Collection: Brno University of Technology (VUT): Digital Library / Vysoké učení technické v Brně: Digitální knihovně
Subject Terms: LDPC code shortening, System on a Chip, fixed nodes decoder, Adaptive Coding and Modulation
Description: This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation.
Document Type: article in journal/newspaper
File Description: text; 783-790; application/pdf
Language: English
Relation: Radioengineering; http://www.radioeng.cz/fulltexts/2015/15_03_0783_0790.pdf; http://hdl.handle.net/11012/51745
DOI: 10.13164/re.2015.0783
Availability: http://hdl.handle.net/11012/51745
https://doi.org/10.13164/re.2015.0783
Rights: Creative Commons Attribution 3.0 Unported License ; http://creativecommons.org/licenses/by/3.0/ ; openAccess
Accession Number: edsbas.C1DFDFE6
Database: BASE
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IllustrationInfo
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  Label: Title
  Group: Ti
  Data: Analysis of Minimal LDPC Decoder System on a Chip Implementation
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Palenik%2C+Tomas%22">Palenik, Tomas</searchLink><br /><searchLink fieldCode="AR" term="%22Farkas%2C+Peter%22">Farkas, Peter</searchLink><br /><searchLink fieldCode="AR" term="%22Rakus%2C+Martin%22">Rakus, Martin</searchLink><br /><searchLink fieldCode="AR" term="%22Dobos%2C+Jan%22">Dobos, Jan</searchLink>
– Name: Publisher
  Label: Publisher Information
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  Data: Společnost pro radioelektronické inženýrství
– Name: DatePubCY
  Label: Publication Year
  Group: Date
  Data: 2015
– Name: Subset
  Label: Collection
  Group: HoldingsInfo
  Data: Brno University of Technology (VUT): Digital Library / Vysoké učení technické v Brně: Digitální knihovně
– Name: Subject
  Label: Subject Terms
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22LDPC+code+shortening%22">LDPC code shortening</searchLink><br /><searchLink fieldCode="DE" term="%22System+on+a+Chip%22">System on a Chip</searchLink><br /><searchLink fieldCode="DE" term="%22fixed+nodes+decoder%22">fixed nodes decoder</searchLink><br /><searchLink fieldCode="DE" term="%22Adaptive+Coding+and+Modulation%22">Adaptive Coding and Modulation</searchLink>
– Name: Abstract
  Label: Description
  Group: Ab
  Data: This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation.
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  Data: text; 783-790; application/pdf
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  Data: English
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  Data: Radioengineering; http://www.radioeng.cz/fulltexts/2015/15_03_0783_0790.pdf; http://hdl.handle.net/11012/51745
– Name: DOI
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  Data: 10.13164/re.2015.0783
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  Data: http://hdl.handle.net/11012/51745<br />https://doi.org/10.13164/re.2015.0783
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  Data: Creative Commons Attribution 3.0 Unported License ; http://creativecommons.org/licenses/by/3.0/ ; openAccess
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  Data: edsbas.C1DFDFE6
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      – Text: English
    Subjects:
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      – SubjectFull: System on a Chip
        Type: general
      – SubjectFull: fixed nodes decoder
        Type: general
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            NameFull: Dobos, Jan
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