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Analysis of Minimal LDPC Decoder System on a Chip Implementation

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Bibliographic Details
Title: Analysis of Minimal LDPC Decoder System on a Chip Implementation
Authors: Palenik, Tomas, Farkas, Peter, Rakus, Martin, Dobos, Jan
Publisher Information: Společnost pro radioelektronické inženýrství
Publication Year: 2015
Collection: Brno University of Technology (VUT): Digital Library / Vysoké učení technické v Brně: Digitální knihovně
Subject Terms: LDPC code shortening, System on a Chip, fixed nodes decoder, Adaptive Coding and Modulation
Description: This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation.
Document Type: article in journal/newspaper
File Description: text; 783-790; application/pdf
Language: English
Relation: Radioengineering; http://www.radioeng.cz/fulltexts/2015/15_03_0783_0790.pdf; http://hdl.handle.net/11012/51745
DOI: 10.13164/re.2015.0783
Availability: http://hdl.handle.net/11012/51745
https://doi.org/10.13164/re.2015.0783
Rights: Creative Commons Attribution 3.0 Unported License ; http://creativecommons.org/licenses/by/3.0/ ; openAccess
Accession Number: edsbas.C1DFDFE6
Database: BASE
Description
Abstract:This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation.
DOI:10.13164/re.2015.0783