Towards a java bytecodes compiler for nios II soft-core processor
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| Titel: | Towards a java bytecodes compiler for nios II soft-core processor |
|---|---|
| Autoren: | Lima, Willian S., Lobato, Renata S., Manacero, Aleardo, Spolon, Roberta |
| Weitere Verfasser: | Universidade Estadual Paulista (UNESP) |
| Publikationsjahr: | 2014 |
| Bestand: | Universidade Estadual Paulista São Paulo: Acervo Digital da UNESP / São Paulo State University |
| Schlagwörter: | Bytecodes, Control flows, Dependence graphs, Instruction set, Java bytecodes, NIOS II, Reconfigurable architecture, Reconfigurable computing, Reconfigurable devices, Research topics, Soft-core processors, Source codes, Building codes, Computer architecture, High level languages, Program compilers |
| Beschreibung: | Reconfigurable computing is one of the most recent research topics in computer science. The Altera - Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs. © 2009 IEEE. |
| Publikationsart: | other/unknown material |
| Sprache: | English |
| Relation: | Proceedings - IEEE Symposium on Computers and Communications; http://hdl.handle.net/11449/71241; http://acervodigital.unesp.br/handle/11449/71241; WOS:000277119300017; http://dx.doi.org/10.1109/ISCC.2009.5202253 |
| DOI: | 10.1109/ISCC.2009.5202253 |
| Verfügbarkeit: | http://acervodigital.unesp.br/handle/11449/71241 http://hdl.handle.net/11449/71241 https://doi.org/10.1109/ISCC.2009.5202253 |
| Rights: | info:eu-repo/semantics/closedAccess |
| Dokumentencode: | edsbas.BB586DB0 |
| Datenbank: | BASE |
Nájsť tento článok vo Web of Science | Abstract: | Reconfigurable computing is one of the most recent research topics in computer science. The Altera - Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs. © 2009 IEEE. |
|---|---|
| DOI: | 10.1109/ISCC.2009.5202253 |