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Diseño de una metodología de verificación para el uso de scripts de Python compatibles para un entorno UVM y un entorno de verificación física de un ASIC ; Design of a verification methodology for the use of compatible Python scripts for a UVM environment and a physical verification environment for an ASIC

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Title: Diseño de una metodología de verificación para el uso de scripts de Python compatibles para un entorno UVM y un entorno de verificación física de un ASIC ; Design of a verification methodology for the use of compatible Python scripts for a UVM environment and a physical verification environment for an ASIC
Authors: Fernández Bravo, Álvaro
Contributors: Monzó Ferrer, José María, Carreras Areny, Judit, Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica, Universitat Politècnica de València. Escuela Técnica Superior de Ingenieros de Telecomunicación - Escola Tècnica Superior d'Enginyers de Telecomunicació
Source: Repositorio Institucional de la Universitat Politècnica de València
Publisher Information: Universitat Politècnica de València
Publication Year: 2021
Subject Terms: archi, geo
Description: [EN] This Master's Thesis has been developed within the company Maxlinear. Its main objective is to develop a methodology that allows the use of the Python programming language in a UVM verification environment. This enables the creation of a set of Python scripts for ASIC verification in a UVM environment, which will later be used in a real test environment, using the same verification tests on the ASIC at RTL level and on the ASIC already built. This methodology has been developed with the objective of verifying the ASIC, once built, in the shortest possible time. The verification in a UVM environment provides greater control in the generation of test situations and in the automatic verification of the correct operation of all the ASIC signals. In addition, the methodology proposed in this Thesis allows to verify the Python scripts themselves before being used in a real test environment. This facilitates the verification of the test environment prior to chip fabrication, eliminating the need for FPGA implementation and verification, which is time-consuming and sometimes incompatible with certain designs. To develop this new methodology, it is necessary to export a series of functions or tasks defined in SystemVerilog to Python. For this purpose, the DPI (Direct Programming Interface) between SystemVerilog and the C language has been used, which allows calling C functions from SystemVerilog and exporting others from SystemVerilog to be called from C. Subsequently, using the SWIG (Simplified Wrapper and Interface Generator) tool, a Python test bench will be generated that will allow access to the functions generated in C that communicate with the UVM test bench or with the physical test bench. TFGM ; [ES] El presente Trabajo Fin de Máster ha sido desarrollado dentro de la empresa Maxlinear. Su objetivo principal es desarrollar una metodología que permita el uso del lenguaje de programación Python en un entorno de verificación UVM. Esto posibilita la creación de un conjunto de scripts de Python para la ...
Document Type: thesis
Language: Spanish; Castilian
Relation: http://hdl.handle.net/10251/174412
Availability: http://hdl.handle.net/10251/174412
Rights: other
Accession Number: edsbas.8DA96F79
Database: BASE
Description
Abstract:[EN] This Master's Thesis has been developed within the company Maxlinear. Its main objective is to develop a methodology that allows the use of the Python programming language in a UVM verification environment. This enables the creation of a set of Python scripts for ASIC verification in a UVM environment, which will later be used in a real test environment, using the same verification tests on the ASIC at RTL level and on the ASIC already built. This methodology has been developed with the objective of verifying the ASIC, once built, in the shortest possible time. The verification in a UVM environment provides greater control in the generation of test situations and in the automatic verification of the correct operation of all the ASIC signals. In addition, the methodology proposed in this Thesis allows to verify the Python scripts themselves before being used in a real test environment. This facilitates the verification of the test environment prior to chip fabrication, eliminating the need for FPGA implementation and verification, which is time-consuming and sometimes incompatible with certain designs. To develop this new methodology, it is necessary to export a series of functions or tasks defined in SystemVerilog to Python. For this purpose, the DPI (Direct Programming Interface) between SystemVerilog and the C language has been used, which allows calling C functions from SystemVerilog and exporting others from SystemVerilog to be called from C. Subsequently, using the SWIG (Simplified Wrapper and Interface Generator) tool, a Python test bench will be generated that will allow access to the functions generated in C that communicate with the UVM test bench or with the physical test bench. TFGM ; [ES] El presente Trabajo Fin de Máster ha sido desarrollado dentro de la empresa Maxlinear. Su objetivo principal es desarrollar una metodología que permita el uso del lenguaje de programación Python en un entorno de verificación UVM. Esto posibilita la creación de un conjunto de scripts de Python para la ...