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Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

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Titel: Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing
Autoren: Harb, Hassan, Al Ghouwayel, Ali Chamas, Conde-Canencia, Laura, Marchand, Cedric, Boutillon, Emmanuel
Quelle: WoS
Verlagsinformationen: SPRINGER
New York
Publikationsjahr: 2022
Bestand: Ecole Polytechnique Fédérale Lausanne (EPFL): Infoscience
Schlagwörter: Computer Science, Information Systems, Engineering, Electrical & Electronic, channel coding, decoder implementation, asic, non-binary ldpc, min-sum, parity check, low-complexity, nonbinary, codes, architecture, design
Beschreibung: This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10(-3). ; TCL
Publikationsart: article in journal/newspaper
Sprache: unknown
ISSN: 1939-8018
1939-8115
Relation: https://infoscience.epfl.ch/record/295506/files/s11265-022-01795-y.pdf; Journal Of Signal Processing Systems For Signal Image And Video Technology; https://infoscience.epfl.ch/handle/20.500.14299/189602; WOS:000828958200001
DOI: 10.1007/s11265-022-01795-y
Verfügbarkeit: https://doi.org/10.1007/s11265-022-01795-y
https://infoscience.epfl.ch/handle/20.500.14299/189602
https://hdl.handle.net/20.500.14299/189602
Dokumentencode: edsbas.7F84B1D6
Datenbank: BASE
Beschreibung
Abstract:This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10(-3). ; TCL
ISSN:19398018
19398115
DOI:10.1007/s11265-022-01795-y